| 6d06fc4e | 03-Apr-2024 |
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> |
clk: renesas: r9a07g043: Add clock and reset entry for PLIC
[ Upstream commit 44019387fce230beda35b83da3a2c9fc5787704e ]
Add the missing clock and reset entry for PLIC. Also add
R9A07G043_NCEPLIC_A
clk: renesas: r9a07g043: Add clock and reset entry for PLIC
[ Upstream commit 44019387fce230beda35b83da3a2c9fc5787704e ]
Add the missing clock and reset entry for PLIC. Also add
R9A07G043_NCEPLIC_ACLK to the critical clocks list.
Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240403200952.633084-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| 427322dc | 25-Jan-2024 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
[ Upstream commit d1b32a83a02d9433dbd8c5f4d6fc44aa597755bd ]
According to the R-Car S4 Series Hardware User’s Manual Rev.0.81, the
parent clock
clk: renesas: r8a779f0: Correct PFC/GPIO parent clock
[ Upstream commit d1b32a83a02d9433dbd8c5f4d6fc44aa597755bd ]
According to the R-Car S4 Series Hardware User’s Manual Rev.0.81, the
parent clock of the Pin Function (PFC/GPIO) module clock is the CP
clock.
As this clock is not documented to exist on R-Car S4, use the CPEX clock
instead.
Fixes: 73421f2a48e6bd1d ("clk: renesas: r8a779f0: Add PFC clock")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f88ec4aede0eaf0107c8bb7b28ba719ac6cd418f.1706197415.git.geert+renesas@glider.be
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| 0afe652a | 07-Dec-2023 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
clk: renesas: rzg2l: Check reset monitor registers
[ Upstream commit da235d2fac212d0add570e755feb1167a830bc99 ]
The hardware manual of both RZ/G2L and RZ/G3S specifies that the reset
monitor regist
clk: renesas: rzg2l: Check reset monitor registers
[ Upstream commit da235d2fac212d0add570e755feb1167a830bc99 ]
The hardware manual of both RZ/G2L and RZ/G3S specifies that the reset
monitor registers need to be interrogated when the reset signals are
toggled (chapters "Procedures for Supplying and Stopping Reset Signals"
and "Procedure for Activating Modules"). Without this, there is a
chance that different modules (e.g. Ethernet) are not ready after their
reset signal is toggled, leading to failures (on probe or resume from
deep sleep states).
The same indications are available for RZ/V2M for TYPE-B reset controls.
Fixes: ef3c613ccd68 ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Fixes: 8090bea32484 ("clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231207070700.4156557-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| a8454ab7 | 29-Sep-2023 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
clk: renesas: rzg2l: Fix computation formula
[ Upstream commit a2b23159499efd36b2d63b3c4534075d12ddc97a ]
According to the hardware manual for RZ/G2L
(r01uh0914ej0130-rzg2l-rzg2lc.pdf), the computa
clk: renesas: rzg2l: Fix computation formula
[ Upstream commit a2b23159499efd36b2d63b3c4534075d12ddc97a ]
According to the hardware manual for RZ/G2L
(r01uh0914ej0130-rzg2l-rzg2lc.pdf), the computation formula for PLL rate
is as follows:
Fout = ((m + k/65536) * Fin) / (p * 2^s)
and k has values in the range [-32768, 32767]. Dividing k by 65536 with
integer arithmetic gives zero all the time, causing slight differences
b/w what has been set vs. what is displayed. Thus, get rid of this and
decompose the formula before dividing k by 65536.
Fixes: ef3c613ccd68a ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-6-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| da8862f7 | 11-Sep-2023 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields
[ Upstream commit 72977f07b035e488c3f1928832a1616c6cae7278 ]
Use FIELD_GET() for PLL register fields. This is its purpose.
Signed-off-
clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields
[ Upstream commit 72977f07b035e488c3f1928832a1616c6cae7278 ]
Use FIELD_GET() for PLL register fields. This is its purpose.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230912045157.177966-14-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Stable-dep-of: a2b23159499e ("clk: renesas: rzg2l: Fix computation formula")
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| cd7231cd | 29-Sep-2023 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
clk: renesas: rzg2l: Trust value returned by hardware
[ Upstream commit bf51d3b2d048c312764a55d91d67a85ee5535e31 ]
The onitial value of the CPG_PL2SDHI_DSEL bits 0..1 or 4..6 is 01b. The
hardware
clk: renesas: rzg2l: Trust value returned by hardware
[ Upstream commit bf51d3b2d048c312764a55d91d67a85ee5535e31 ]
The onitial value of the CPG_PL2SDHI_DSEL bits 0..1 or 4..6 is 01b. The
hardware user's manual (r01uh0914ej0130-rzg2l-rzg2lc.pdf) specifies that
setting 0 is prohibited. Hence rzg2l_cpg_sd_clk_mux_get_parent() should
just read CPG_PL2SDHI_DSEL, trust the value, and return the proper clock
parent index based on the value read.
Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-5-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| f9290517 | 29-Sep-2023 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
clk: renesas: rzg2l: Lock around writes to mux register
[ Upstream commit d2692ed490e680a41401cef879adebcfafb4298f ]
The SD MUX output (SD0) is further divided by 4 in G2{L,UL}. The
divided clock
clk: renesas: rzg2l: Lock around writes to mux register
[ Upstream commit d2692ed490e680a41401cef879adebcfafb4298f ]
The SD MUX output (SD0) is further divided by 4 in G2{L,UL}. The
divided clock is SD0_DIV4. SD0_DIV4 is registered with
CLK_SET_RATE_PARENT which means a rate request for it is propagated to
the MUX and could reach rzg2l_cpg_sd_clk_mux_set_parent() concurrently
with the users of SD0.
Add proper locking to avoid concurrent accesses on SD MUX set rate
registers.
Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-4-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| 75b64863 | 29-Sep-2023 |
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> |
clk: renesas: rzg2l: Wait for status bit of SD mux before continuing
[ Upstream commit 549f4ae2601f968e2474c6031fb4799468882f64 ]
The hardware user manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.p
clk: renesas: rzg2l: Wait for status bit of SD mux before continuing
[ Upstream commit 549f4ae2601f968e2474c6031fb4799468882f64 ]
The hardware user manual for RZ/G2L (r01uh0914ej0130-rzg2l-rzg2lc.pdf,
chapter 7.4.7 Procedure for Switching Clocks by the Dynamic Switching
Frequency Selectors) specifies that we need to check CPG_PL2SDHI_DSEL
for SD clock switching status.
Fixes: eaff33646f4cb ("clk: renesas: rzg2l: Add SDHI clk mux support")
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929053915.1530607-3-claudiu.beznea@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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| 708cb698 | 31-Jul-2023 |
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
clk: renesas: rcar-gen3: Add ADG clocks
R-Car Sound needs to enable "ADG" on RMSTPCR9/SMSTPCR9 bit 22 to use
clk_i which came from the internal S0D4 or ZA2 clock.
Signed-off-by: Kuninori Morimoto <
clk: renesas: rcar-gen3: Add ADG clocks
R-Car Sound needs to enable "ADG" on RMSTPCR9/SMSTPCR9 bit 22 to use
clk_i which came from the internal S0D4 or ZA2 clock.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Vincenzo De Michele <vincenzo.michele@davinci.de> # R-Car M3-N
Tested-by: Patrick Keil <patrick.keil@conti-engineering.com> # R-Car M3-N
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/87pm47prox.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87o7jrpros.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87mszbpron.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87leevproh.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87jzufprod.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87il9zpro8.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87h6pjpro4.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87fs53prny.wl-kuninori.morimoto.gx@renesas.com
Link: https://lore.kernel.org/r/87edknprnt.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| dec57795 | 17-Jul-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a77965: Add 3DGE and ZG support
The 3DGE and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kerne
clk: renesas: r8a77965: Add 3DGE and ZG support
The 3DGE and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1767d01cfffd7490861f2cf6ad6c0df100916907.1689599217.git.geert+renesas@glider.be
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| fd177b9a | 17-Jul-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a7796: Add 3DGE and ZG support
The 3DGE and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel
clk: renesas: r8a7796: Add 3DGE and ZG support
The 3DGE and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/291462bea7ffc13f8218c1901dc384b576bfc2d6.1689599217.git.geert+renesas@glider.be
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| eba0214d | 17-Jul-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: r8a7795: Add 3DGE and ZG support
The 3DGE and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel
clk: renesas: r8a7795: Add 3DGE and ZG support
The 3DGE and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/36096e2df2a54516fadd1978c47fc7de354abc26.1689599217.git.geert+renesas@glider.be
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| 89feed8e | 09-Jun-2023 |
Geert Uytterhoeven <geert+renesas@glider.be> |
clk: renesas: emev2: Remove obsolete clkdev registration
EMMA Mobile EV2 is a multi-platform/CCF-only platform, registering all
devices from DT, so we can remove the registration of clkdevs.
Signed
clk: renesas: emev2: Remove obsolete clkdev registration
EMMA Mobile EV2 is a multi-platform/CCF-only platform, registering all
devices from DT, so we can remove the registration of clkdevs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Niklas Söderlund <niklas.soderlund@ragnatech.se>
Link: https://lore.kernel.org/r/f54a30d7a9e2aa075d462db701a60b0b59c6ad0b.1686325857.git.geert+renesas@glider.be
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| 2fd3f06b | 14-Jul-2023 |
Biju Das <biju.das.jz@bp.renesas.com> |
clk: renesas: r9a07g043: Add MTU3a clock and reset entry
Add MTU3a clock and reset entry to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+r
clk: renesas: r9a07g043: Add MTU3a clock and reset entry
Add MTU3a clock and reset entry to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230714075649.146978-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| bbceb13c | 07-Jul-2023 |
Christophe JAILLET <christophe.jaillet@wanadoo.fr> |
clk: renesas: rzg2l: Simplify .determine_rate()
rzg2l_cpg_sd_clk_mux_determine_rate() is the same as
__clk_mux_determine_rate_closest(), so use the latter to save some LoC.
Signed-off-by: Christoph
clk: renesas: rzg2l: Simplify .determine_rate()
rzg2l_cpg_sd_clk_mux_determine_rate() is the same as
__clk_mux_determine_rate_closest(), so use the latter to save some LoC.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/fed02e0325275df84e2d76f8c481e40e7023cbd9.1688760372.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| 63370298 | 22-Jun-2023 |
Fabrizio Castro <fabrizio.castro.jz@renesas.com> |
clk: renesas: r9a09g011: Add CSI related clocks
The Renesas RZ/V2M SoC comes with 6 CSI IPs (CSI0, CSI1, CSI2
CSI3, CSI4, and CSI5), however Linux is only allowed control
of CSI0 and CSI4.
CSI0 shar
clk: renesas: r9a09g011: Add CSI related clocks
The Renesas RZ/V2M SoC comes with 6 CSI IPs (CSI0, CSI1, CSI2
CSI3, CSI4, and CSI5), however Linux is only allowed control
of CSI0 and CSI4.
CSI0 shares its reset and PCLK lines with CSI1, CSI2, and CSI3.
CSI4 shares its reset and PCLK lines with CSI5.
This commit adds support for the relevant clocks.
Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230622113341.657842-3-fabrizio.castro.jz@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| adf6b916 | 17-Jun-2023 |
Adam Ford <aford173@gmail.com> |
clk: renesas: r8a774b1: Add 3DGE and ZG support
The 3DGE and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert
clk: renesas: r8a774b1: Add 3DGE and ZG support
The 3DGE and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230617150302.38477-4-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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| 2f77da09 | 17-Jun-2023 |
Adam Ford <aford173@gmail.com> |
clk: renesas: r8a774e1: Add 3DGE and ZG support
The 3DGE and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert
clk: renesas: r8a774e1: Add 3DGE and ZG support
The 3DGE and ZG clocks are necessary to support the 3D graphics.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230617150302.38477-3-aford173@gmail.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
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