| 3b99cd27 | 12-Aug-2023 |
Duje Mihanović <duje.mihanovic@skole.hr> |
clk: pxa910: Move number of clocks to driver source
The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.
Move thi
clk: pxa910: Move number of clocks to driver source
The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.
Move this number of clocks into the driver source.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-4-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
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| 87f06247 | 12-Aug-2023 |
Duje Mihanović <duje.mihanovic@skole.hr> |
clk: pxa1928: Move number of clocks to driver source
The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.
Move th
clk: pxa1928: Move number of clocks to driver source
The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.
Move this number of clocks into the driver source.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-3-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
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| 51fa6aa5 | 12-Aug-2023 |
Duje Mihanović <duje.mihanovic@skole.hr> |
clk: pxa168: Move number of clocks to driver source
The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.
Move thi
clk: pxa168: Move number of clocks to driver source
The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.
Move this number of clocks into the driver source.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-2-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
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| 46c13513 | 12-Aug-2023 |
Duje Mihanović <duje.mihanovic@skole.hr> |
clk: mmp2: Move number of clocks to driver source
The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.
Move this
clk: mmp2: Move number of clocks to driver source
The number of clocks should not be in the dt binding as it is not used
by the respective device tree and thus needlessly bloats the ABI.
Move this number of clocks into the driver source.
Signed-off-by: Duje Mihanović <duje.mihanovic@skole.hr>
Link: https://lore.kernel.org/r/20230812-mmp-nr-clks-v2-1-f9271bd7eaa5@skole.hr
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
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| e11a47f5 | 12-Jun-2022 |
Doug Brown <doug@schmorgal.com> |
clk: mmp: pxa168: control shared SDH bits with separate clock
The PXA168 has a peculiar setup with the AXI clock enable control for
the SDHC controllers. The bits in the SDH0 register control the AX
clk: mmp: pxa168: control shared SDH bits with separate clock
The PXA168 has a peculiar setup with the AXI clock enable control for
the SDHC controllers. The bits in the SDH0 register control the AXI
clock enable for both SDH0 and SDH1. Likewise, the bits in the SDH2
register control both SDH2 and SDH3. This is modeled with two new
parentless clocks that control the shared bits.
Previously, SDH0 had to be enabled in order for SDH1 to be used, and
when SDH1 was enabled, unused bits in the SDH1 register were being
controlled. This fixes those issues. A future commit will add support
for these new shared clocks to be enabled by the PXA168 SDHC driver.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-13-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| 69ec8691 | 12-Jun-2022 |
Doug Brown <doug@schmorgal.com> |
clk: mmp: pxa168: add clocks for SDH2 and SDH3
The PXA168 has four SDHC peripherals. This commit adds the last two.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20
clk: mmp: pxa168: add clocks for SDH2 and SDH3
The PXA168 has four SDHC peripherals. This commit adds the last two.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-11-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
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| d4161f7e | 12-Jun-2022 |
Doug Brown <doug@schmorgal.com> |
clk: mmp: pxa168: fix GPIO clock enable bits
According to the datasheet, only bit 0 of APBC_GPIO should be controlled
for the clock enable. Bit 1 is marked as reserved (always write 0).
Signed-off-
clk: mmp: pxa168: fix GPIO clock enable bits
According to the datasheet, only bit 0 of APBC_GPIO should be controlled
for the clock enable. Bit 1 is marked as reserved (always write 0).
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-9-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| 7fad6b75 | 12-Jun-2022 |
Doug Brown <doug@schmorgal.com> |
clk: mmp: pxa168: add muxes for more peripherals
The TWSI, KPC, PWM, and DFC peripherals didn't have their muxes modeled
in the code, but the PXA168 datasheet shows that they are indeed muxed:
- TW
clk: mmp: pxa168: add muxes for more peripherals
The TWSI, KPC, PWM, and DFC peripherals didn't have their muxes modeled
in the code, but the PXA168 datasheet shows that they are indeed muxed:
- TWSI can be 31.2 MHz or 62.4 MHz
- KPC can be 32 kHz, 16 kHz, or 26 MHz
- PWM can be 13 MHz or 32 kHz
- DFC can be 156 MHz or 78 MHz
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-8-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| 30c03682 | 12-Jun-2022 |
Doug Brown <doug@schmorgal.com> |
clk: mmp: pxa168: fix incorrect parent clocks
The UART, SDHC, LCD, and CCIC peripherals' muxed parent clocks didn't
match the information provided by the PXA168 datasheet:
- The UART clocks can be
clk: mmp: pxa168: fix incorrect parent clocks
The UART, SDHC, LCD, and CCIC peripherals' muxed parent clocks didn't
match the information provided by the PXA168 datasheet:
- The UART clocks can be 58.5 MHz or the UART PLL. Previously, the first
mux option was being calculated as 117 MHz, confirmed on hardware to
be incorrect.
- The SDHC clocks can be 48 MHz, 52 MHz, or 78 MHz. Previously, 48 MHz
and 52 MHz were swapped. 78 MHz wasn't listed as an option.
- The LCD clock can be 624 MHz or 312 Mhz. Previously, it was being
calculated as 312 MHz or 52 MHz.
- The CCIC clock can be 156 MHz or 78 MHz. Previously, it was being
calculated as 312 MHz or 52 MHz.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-7-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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| e2fd64dd | 12-Jun-2022 |
Doug Brown <doug@schmorgal.com> |
clk: mmp: pxa168: fix const-correctness
While working on this series of patches, checkpatch recommended that
an extra const should be added to the mux parent arrays.
Signed-off-by: Doug Brown <doug
clk: mmp: pxa168: fix const-correctness
While working on this series of patches, checkpatch recommended that
an extra const should be added to the mux parent arrays.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-6-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
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| ac1d62c9 | 12-Jun-2022 |
Doug Brown <doug@schmorgal.com> |
clk: mmp: pxa168: add new clocks for peripherals
This commit adds three new clocks that previously didn't exist, but are
needed in order to match the clock parenting as described in the PXA168
datas
clk: mmp: pxa168: add new clocks for peripherals
This commit adds three new clocks that previously didn't exist, but are
needed in order to match the clock parenting as described in the PXA168
datasheet.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-5-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
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| a77a1e2f | 12-Jun-2022 |
Doug Brown <doug@schmorgal.com> |
clk: mmp: pxa168: fix incorrect dividers
These two clocks had multipliers and dividers that didn't match their
names. A subsequent commit goes through all of the existing peripherals
and ensure the
clk: mmp: pxa168: fix incorrect dividers
These two clocks had multipliers and dividers that didn't match their
names. A subsequent commit goes through all of the existing peripherals
and ensure the correct clocks are being used everywhere.
Signed-off-by: Doug Brown <doug@schmorgal.com>
Link: https://lore.kernel.org/r/20220612192937.162952-3-doug@schmorgal.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
show more ...
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