clk: Explicitly include correct DT includes

The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that mer

clk: Explicitly include correct DT includes

The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.

Acked-by: Dinh Nguyen <dinguyen@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> # samsung
Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # versaclock5
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230718143156.1066339-1-robh@kernel.org
Acked-by: Abel Vesa <abel.vesa@linaro.org> #imx
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

show more ...

clk: hi6220: use CLK_OF_DECLARE_DRIVER

As now we also need to probe in the reset driver as well.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Allison Rand

clk: hi6220: use CLK_OF_DECLARE_DRIVER

As now we also need to probe in the reset driver as well.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Allison Randal <allison@lohutok.net>
Cc: Peter Griffin <peter.griffin@linaro.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Link: https://lkml.kernel.org/r/20191001182546.70090-1-john.stultz@linaro.org
[sboyd@kernel.org: Add comment about reset driver]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

show more ...

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of th

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

show more ...

clk: hi6220: mark clock cs_atb_syspll as critical

Clock cs_atb_syspll is pll used for coresight trace bus; when clock
cs_atb_syspll is disabled and operates its child clock node cs_atb
results in sy

clk: hi6220: mark clock cs_atb_syspll as critical

Clock cs_atb_syspll is pll used for coresight trace bus; when clock
cs_atb_syspll is disabled and operates its child clock node cs_atb
results in system hang. So mark clock cs_atb_syspll as critical to
keep it enabled.

Cc: Guodong Xu <guodong.xu@linaro.org>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1504226835-2115-2-git-send-email-leo.yan@linaro.org

show more ...

clk: hi6220: change watchdog clock source

The old code uses tcxo (19.2MHz) as watchdog clock but actually the
watchdog uses 32K clock, as result the watchdog timeout cannot be set
correctly and dela

clk: hi6220: change watchdog clock source

The old code uses tcxo (19.2MHz) as watchdog clock but actually the
watchdog uses 32K clock, as result the watchdog timeout cannot be set
correctly and delay long time to reset SoC.

So this patch is to use 'ref32k' as clock source for watchdog.

Fixes: 72ea48610d43 ("clk: hi6220: Clock driver support for Hisilicon hi6220 SoC")
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

show more ...

clk: hi6220: add acpu clock

Add acpu clock, including sft clock controlling hi6220 coresight module

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Li Pengcheng <lipengcheng8@h

clk: hi6220: add acpu clock

Add acpu clock, including sft clock controlling hi6220 coresight module

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Li Pengcheng <lipengcheng8@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

show more ...

clk: hi6220: add debug APB clock

The debug APB clock is absent in hi6220 driver, so this patch is to add
support for it.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sbo

clk: hi6220: add debug APB clock

The debug APB clock is absent in hi6220 driver, so this patch is to add
support for it.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>

show more ...

clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init

The hi6220-sysctrl and hi6220-mediactrl are not only clock provider but
also reset controller. It worked fine that single

clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init

The hi6220-sysctrl and hi6220-mediactrl are not only clock provider but
also reset controller. It worked fine that single sysctrl/mediactrl
device node in DT can be used to initialize clock driver and populate
platform device for reset controller. But it stops working after
commit 989eafd0b609 ("clk: core: Avoid double initialization of clocks")
gets merged. The commit sets flag OF_POPULATED during clock
initialization to skip the platform device populating for the same
device node. On hi6220, it effectively makes hi6220-sysctrl reset
driver not probe any more.

The patch changes hi6220 sysctrl and mediactrl clock init macro from
CLK_OF_DECLARE to CLK_OF_DECLARE_DRIVER, so that the reset driver using
the same hardware block can continue working.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

show more ...

clk: hi6220: Change syspll and media_syspll clk to 1.19GHz

In the bootloader of HiKey/96boards, syspll and media_syspll clk
was initialized to 1.19GHz. So, here changes it in kernel accordingly.

1.

clk: hi6220: Change syspll and media_syspll clk to 1.19GHz

In the bootloader of HiKey/96boards, syspll and media_syspll clk
was initialized to 1.19GHz. So, here changes it in kernel accordingly.

1.19GHz was chosen over 1.2GHz because at 1.19GHz we get more precise
HDMI pixel clock (1.19G/16 = 74.4MHz) for 1280x720p@60Hz HDMI
(74.25MHz required by standards). Closer pixel clock means better
compatibility to HDMI monitors.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1467189955-21694-1-git-send-email-guodong.xu@linaro.org

show more ...

clk: hi6220: Add RTC clock for pl031

Adds clk support for the pl031 RTC on hi6220

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@ke

clk: hi6220: Add RTC clock for pl031

Adds clk support for the pl031 RTC on hi6220

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
[jstultz: Forward ported, tweaked commit description]
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

show more ...

clk: hisilicon: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Tested-by: Leo Yan <leo.yan@linaro.org>
Cc: Bintian Wang <bintian.wang@huawei.com>
Cc: Zhangfei Gao <zhangfei.

clk: hisilicon: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Tested-by: Leo Yan <leo.yan@linaro.org>
Cc: Bintian Wang <bintian.wang@huawei.com>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

show more ...

clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add on

clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Bintian Wang <bintian.wang@huawei.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Tested-by: Will Deacon <will.deacon@arm.com>
Tested-by: Tyler Baker <tyler.baker@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

show more ...

clk: hi6220: use CLK_OF_DECLARE_DRIVER

As now we also need to probe in the reset driver as well.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.o

clk: hi6220: use CLK_OF_DECLARE_DRIVER

As now we also need to probe in the reset driver as well.

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Allison Randal <allison@lohutok.net>
Cc: Peter Griffin <peter.griffin@linaro.org>
Cc: linux-clk@vger.kernel.org
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Link: https://lkml.kernel.org/r/20191001182546.70090-1-john.stultz@linaro.org
[sboyd@kernel.org: Add comment about reset driver]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

show more ...

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it u

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

Based on 2 normalized pattern(s):

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation

this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

show more ...

clk: hi6220: mark clock cs_atb_syspll as critical

Clock cs_atb_syspll is pll used for coresight trace bus; when clock
cs_atb_syspll is disabled and operates its child clock node cs_atb

clk: hi6220: mark clock cs_atb_syspll as critical

Clock cs_atb_syspll is pll used for coresight trace bus; when clock
cs_atb_syspll is disabled and operates its child clock node cs_atb
results in system hang. So mark clock cs_atb_syspll as critical to
keep it enabled.

Cc: Guodong Xu <guodong.xu@linaro.org>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1504226835-2115-2-git-send-email-leo.yan@linaro.org

show more ...

clk: hi6220: change watchdog clock source

The old code uses tcxo (19.2MHz) as watchdog clock but actually the
watchdog uses 32K clock, as result the watchdog timeout cannot be set
co

clk: hi6220: change watchdog clock source

The old code uses tcxo (19.2MHz) as watchdog clock but actually the
watchdog uses 32K clock, as result the watchdog timeout cannot be set
correctly and delay long time to reset SoC.

So this patch is to use 'ref32k' as clock source for watchdog.

Fixes: 72ea48610d43 ("clk: hi6220: Clock driver support for Hisilicon hi6220 SoC")
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

show more ...

clk: hi6220: add acpu clock

Add acpu clock, including sft clock controlling hi6220 coresight module

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Li Pengc

clk: hi6220: add acpu clock

Add acpu clock, including sft clock controlling hi6220 coresight module

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Li Pengcheng <lipengcheng8@huawei.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

show more ...

clk: hi6220: add debug APB clock

The debug APB clock is absent in hi6220 driver, so this patch is to add
support for it.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-o

clk: hi6220: add debug APB clock

The debug APB clock is absent in hi6220 driver, so this patch is to add
support for it.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>

show more ...

clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init

The hi6220-sysctrl and hi6220-mediactrl are not only clock provider but
also reset controller. It worked fine

clk: hi6220: use CLK_OF_DECLARE_DRIVER for sysctrl and mediactrl clock init

The hi6220-sysctrl and hi6220-mediactrl are not only clock provider but
also reset controller. It worked fine that single sysctrl/mediactrl
device node in DT can be used to initialize clock driver and populate
platform device for reset controller. But it stops working after
commit 989eafd0b609 ("clk: core: Avoid double initialization of clocks")
gets merged. The commit sets flag OF_POPULATED during clock
initialization to skip the platform device populating for the same
device node. On hi6220, it effectively makes hi6220-sysctrl reset
driver not probe any more.

The patch changes hi6220 sysctrl and mediactrl clock init macro from
CLK_OF_DECLARE to CLK_OF_DECLARE_DRIVER, so that the reset driver using
the same hardware block can continue working.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

show more ...

clk: hi6220: Change syspll and media_syspll clk to 1.19GHz

In the bootloader of HiKey/96boards, syspll and media_syspll clk
was initialized to 1.19GHz. So, here changes it in kernel acco

clk: hi6220: Change syspll and media_syspll clk to 1.19GHz

In the bootloader of HiKey/96boards, syspll and media_syspll clk
was initialized to 1.19GHz. So, here changes it in kernel accordingly.

1.19GHz was chosen over 1.2GHz because at 1.19GHz we get more precise
HDMI pixel clock (1.19G/16 = 74.4MHz) for 1280x720p@60Hz HDMI
(74.25MHz required by standards). Closer pixel clock means better
compatibility to HDMI monitors.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xinliang Liu <xinliang.liu@linaro.org>
Signed-off-by: Michael Turquette <mturquette@baylibre.com>
Link: lkml.kernel.org/r/1467189955-21694-1-git-send-email-guodong.xu@linaro.org

show more ...

clk: hi6220: Add RTC clock for pl031

Adds clk support for the pl031 RTC on hi6220

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc:

clk: hi6220: Add RTC clock for pl031

Adds clk support for the pl031 RTC on hi6220

Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
[jstultz: Forward ported, tweaked commit description]
Signed-off-by: John Stultz <john.stultz@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

show more ...

clk: hisilicon: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Tested-by: Leo Yan <leo.yan@linaro.org>
Cc: Bintian Wang <bintian.wang@huawei.com>
Cc:

clk: hisilicon: Remove CLK_IS_ROOT

This flag is a no-op now. Remove usage of the flag.

Tested-by: Leo Yan <leo.yan@linaro.org>
Cc: Bintian Wang <bintian.wang@huawei.com>
Cc: Zhangfei Gao <zhangfei.gao@linaro.org>
Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

show more ...

clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC

clk: hi6220: Clock driver support for Hisilicon hi6220 SoC

Add clock drivers for hi6220 SoC, this driver controls the SoC
registers to supply different clocks to different IPs in the SoC.

We add one divider clock for hi6220 because the divider in hi6220
also has a mask bit but it doesnot obey the rule defined by flag
"CLK_DIVIDER_HIWORD_MASK", we can not get index of the mask bit by
left shift fixed bits (e.g. 16 bits), so we add this divider clock
to handle it.

Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Signed-off-by: Bintian Wang <bintian.wang@huawei.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Tested-by: Will Deacon <will.deacon@arm.com>
Tested-by: Tyler Baker <tyler.baker@linaro.org>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>

show more ...