cache: ax45mp_cache: Align end size to cache boundary in ax45mp_dma_cache_wback()[ Upstream commit 9bd405c48b0ac4de087c0c4440fd79597201b8a7 ]Align the end size to cache boundary size in ax45mp_dm
cache: ax45mp_cache: Align end size to cache boundary in ax45mp_dma_cache_wback()[ Upstream commit 9bd405c48b0ac4de087c0c4440fd79597201b8a7 ]Align the end size to cache boundary size in ax45mp_dma_cache_wback()callback likewise done in ax45mp_dma_cache_inv() callback.Additionally return early in case of start == end.Fixes: d34599bcd2e4 ("cache: Add L2 cache management for Andes AX45MP RISC-V core")Reported-by: Pavel Machek <pavel@denx.de>Link: https://lore.kernel.org/cip-dev/ZYsdKDiw7G+kxQ3m@duo.ucw.cz/Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>Signed-off-by: Conor Dooley <conor.dooley@microchip.com>Signed-off-by: Sasha Levin <sashal@kernel.org>
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riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENTRISCV_NONSTANDARD_CACHE_OPS is also used for the pmem cache maintenancehelpers, which are built into the kernel uncondit
riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENTRISCV_NONSTANDARD_CACHE_OPS is also used for the pmem cache maintenancehelpers, which are built into the kernel unconditionally.Signed-off-by: Christoph Hellwig <hch@lst.de>Acked-by: Conor Dooley <conor.dooley@microchip.com>Link: https://lore.kernel.org/r/20231018052654.50074-2-hch@lst.deSigned-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
cache: Add L2 cache management for Andes AX45MP RISC-V coreI/O Coherence Port (IOCP) provides an AXI interface for connectingexternal non-caching masters, such as DMA controllers. The accessesfro
cache: Add L2 cache management for Andes AX45MP RISC-V coreI/O Coherence Port (IOCP) provides an AXI interface for connectingexternal non-caching masters, such as DMA controllers. The accessesfrom IOCP are coherent with D-Caches and L2 Cache.IOCP is a specification option and is disabled on the Renesas RZ/FiveSoC due to this reason IP blocks using DMA will fail.The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)block that allows dynamic adjustment of memory attributes in the runtime.It contains a configurable amount of PMA entries implemented as CSRregisters to control the attributes of memory locations in interest.Below are the memory attributes supported:* Device, Non-bufferable* Device, bufferable* Memory, Non-cacheable, Non-bufferable* Memory, Non-cacheable, Bufferable* Memory, Write-back, No-allocate* Memory, Write-back, Read-allocate* Memory, Write-back, Write-allocate* Memory, Write-back, Read and Write-allocateMore info about PMA (section 10.3):Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdfAs a workaround for SoCs with IOCP disabled CMO needs to be handled bysoftware. Firstly OpenSBI configures the memory region as"Memory, Non-cacheable, Bufferable" and passes this region as a globalshared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMAallocations happen from this region and synchronization callbacks areimplemented to synchronize when doing DMA transactions.Example PMA region passes as a DT node from OpenSBI: reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; pma_resv0@58000000 { compatible = "shared-dma-pool"; reg = <0x0 0x58000000 0x0 0x08000000>; no-map; linux,dma-default; }; };Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>Reviewed-by: Conor Dooley <conor.dooley@microchip.com>Tested-by: Conor Dooley <conor.dooley@microchip.com> # tyre-kicking on a d1Link: https://lore.kernel.org/r/20230818135723.80612-6-prabhakar.mahadev-lad.rj@bp.renesas.comSigned-off-by: Palmer Dabbelt <palmer@rivosinc.com>