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Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45 |
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| #
27eb552e |
| 10-Aug-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: enable EMAC1
Enable the second MAC on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.co
arm64: dts: qcom: sa8775p-ride: enable EMAC1
Enable the second MAC on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-10-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
show more ...
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| #
fdc051e3 |
| 10-Aug-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: add an alias for ethernet0
Once we add a second ethernet node, the MDIO bus names will conflict
unless we provide aliases. Add one for the existing ethernet node.
Si
arm64: dts: qcom: sa8775p-ride: add an alias for ethernet0
Once we add a second ethernet node, the MDIO bus names will conflict
unless we provide aliases. Add one for the existing ethernet node.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-9-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
show more ...
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| #
f8be0c50 |
| 10-Aug-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: sort aliases alphabetically
For improved readability order the aliases alphabetically for
sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linar
arm64: dts: qcom: sa8775p-ride: sort aliases alphabetically
For improved readability order the aliases alphabetically for
sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-8-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
show more ...
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| #
1a00a068 |
| 10-Aug-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: add the second SGMII PHY
Add a second SGMII PHY that will be used by EMAC1 on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Revie
arm64: dts: qcom: sa8775p-ride: add the second SGMII PHY
Add a second SGMII PHY that will be used by EMAC1 on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-7-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
show more ...
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| #
1e7ef41b |
| 10-Aug-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: index the first SGMII PHY
We'll be adding a second SGMII PHY on the same MDIO bus, so let's index
the first one for better readability.
Signed-off-by: Bartosz Golasz
arm64: dts: qcom: sa8775p-ride: index the first SGMII PHY
We'll be adding a second SGMII PHY on the same MDIO bus, so let's index
the first one for better readability.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-6-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
show more ...
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| #
5255901f |
| 10-Aug-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: move the reset-gpios property of the PHY
Device-tree bindings for MDIO define per-PHY reset-gpios as well as a
global reset-gpios property at the MDIO node level whic
arm64: dts: qcom: sa8775p-ride: move the reset-gpios property of the PHY
Device-tree bindings for MDIO define per-PHY reset-gpios as well as a
global reset-gpios property at the MDIO node level which controls all
devices on the bus. The latter is most likely a workaround for the
chicken-and-egg problem where we cannot read the ID of the PHY before
bringing it out of reset but we cannot bring it out of reset until we've
read its ID.
I have proposed a comprehensive solution for this problem in 2020 but it
never got upstream. We do however have workaround in place which allows
us to hard-code the PHY id in the compatible property, thus skipping the
ID scanning.
Let's make the device-tree for sa8775p-ride slightly more correct by
moving the reset-gpios property to the PHY node with its ID put into the
PHY node's compatible.
Link: https://lore.kernel.org/all/20200622093744.13685-1-brgl@bgdev.pl/
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-5-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
show more ...
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| #
6ca89cc6 |
| 10-Aug-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: enable the second SerDes PHY
Enable the second SerDes PHY on sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Revi
arm64: dts: qcom: sa8775p-ride: enable the second SerDes PHY
Enable the second SerDes PHY on sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-4-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
show more ...
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|
Revision tags: v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40 |
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| #
bf3ee3db |
| 21-Jul-2023 |
Mrinmay Sarkar <quic_msarkar@quicinc.com> |
arm64: dts: qcom: sa8775p-ride: enable pcie nodes
Enable pcie0, pcie1 nodes and their respective phy's.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Link: https://lore.kernel.org/r/1689
arm64: dts: qcom: sa8775p-ride: enable pcie nodes
Enable pcie0, pcie1 nodes and their respective phy's.
Signed-off-by: Mrinmay Sarkar <quic_msarkar@quicinc.com>
Link: https://lore.kernel.org/r/1689960276-29266-5-git-send-email-quic_msarkar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
show more ...
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Revision tags: v6.1.39 |
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| #
e608d16e |
| 11-Jul-2023 |
Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com> |
arm64: dts: qcom: sa8775p-ride: Update L4C parameters
L4c is the supply for UFS vccq, As per UFS spec range of vccq is
1.14V to 1.26V, There are stability issues when operating at
marginal voltage.
arm64: dts: qcom: sa8775p-ride: Update L4C parameters
L4c is the supply for UFS vccq, As per UFS spec range of vccq is
1.14V to 1.26V, There are stability issues when operating at
marginal voltage. Hence configure the min and max vccq voltages
to 1.2V.
Signed-off-by: Naveen Kumar Goud Arepalli <quic_narepall@quicinc.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230711105915.30581-1-quic_narepall@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
show more ...
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|
Revision tags: v6.1.38, v6.1.37, v6.1.36, v6.4 |
|
| #
120ab6c0 |
| 22-Jun-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: enable ethernet0
Enable the first 1Gb ethernet port on sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-b
arm64: dts: qcom: sa8775p-ride: enable ethernet0
Enable the first 1Gb ethernet port on sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230622120142.218055-6-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
show more ...
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| #
48c99529 |
| 22-Jun-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: add pin functions for ethernet0
Add the MDC and MDIO pin functions for ethernet0 on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
arm64: dts: qcom: sa8775p-ride: add pin functions for ethernet0
Add the MDC and MDIO pin functions for ethernet0 on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230622120142.218055-5-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
show more ...
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| #
5ef26fb8 |
| 22-Jun-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: enable the SerDes PHY
Enable the internal PHY on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad
arm64: dts: qcom: sa8775p-ride: enable the SerDes PHY
Enable the internal PHY on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230622120142.218055-4-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
show more ...
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|
Revision tags: v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31 |
|
| #
a1f6bef2 |
| 26-May-2023 |
Shazad Hussain <quic_shazhuss@quicinc.com> |
arm64: dts: qcom: sa8775p-ride: enable i2c11
This enables the i2c11 node on sa8775p-ride board for A2B controller
and audio port expander.
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
arm64: dts: qcom: sa8775p-ride: enable i2c11
This enables the i2c11 node on sa8775p-ride board for A2B controller
and audio port expander.
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230526133122.16443-6-quic_shazhuss@quicinc.com
show more ...
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|
Revision tags: v6.1.30, v6.1.29, v6.1.28, v6.1.27 |
|
| #
4eefaf51 |
| 28-Apr-2023 |
Shazad Hussain <quic_shazhuss@quicinc.com> |
arm64: dts: qcom: sa8775p-ride: enable USB nodes
Enable usb0, usb1 and usb2 nodes and their respective phy's.
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Reviewed-by: Dmitry Baryshkov
arm64: dts: qcom: sa8775p-ride: enable USB nodes
Enable usb0, usb1 and usb2 nodes and their respective phy's.
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Adrien Thierry <athierry@redhat.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230428130824.23803-7-quic_shazhuss@quicinc.com
show more ...
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Revision tags: v6.1.26, v6.3, v6.1.25, v6.1.24 |
|
| #
35c45a11 |
| 11-Apr-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: enable UFS
Enable the UFS and its PHY on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@
arm64: dts: qcom: sa8775p-ride: enable UFS
Enable the UFS and its PHY on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230411130446.401440-6-brgl@bgdev.pl
show more ...
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| #
27eba112 |
| 06-Apr-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: add PMIC regulators
Add PMIC regulators for sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybc
arm64: dts: qcom: sa8775p-ride: add PMIC regulators
Add PMIC regulators for sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406192811.460888-4-brgl@bgdev.pl
show more ...
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Revision tags: v6.1.23, v6.1.22 |
|
| #
81767c15 |
| 27-Mar-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs
Set line names for GPIO lines exposed by PMICs on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org
arm64: dts: qcom: sa8775p-ride: set gpio-line-names for PMIC GPIOs
Set line names for GPIO lines exposed by PMICs on sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-16-brgl@bgdev.pl
show more ...
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| #
634a3de3 |
| 27-Mar-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p: add support for the on-board PMICs
Add a new .dtsi file for sa8775p PMICs and add the four PMICs interfaced
to the SoC via SPMI. Enable the PMICs for sa8775p-ride.
Signed
arm64: dts: qcom: sa8775p: add support for the on-board PMICs
Add a new .dtsi file for sa8775p PMICs and add the four PMICs interfaced
to the SoC via SPMI. Enable the PMICs for sa8775p-ride.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230327125316.210812-8-brgl@bgdev.pl
show more ...
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|
Revision tags: v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16 |
|
| #
e1988af7 |
| 09-Mar-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: enable the BT UART port
Enable the high-speed UART port connected to the Bluetooth controller on
the sa8775p-adp development board.
Signed-off-by: Bartosz Golaszewsk
arm64: dts: qcom: sa8775p-ride: enable the BT UART port
Enable the high-speed UART port connected to the Bluetooth controller on
the sa8775p-adp development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-10-brgl@bgdev.pl
show more ...
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| #
4b6c4249 |
| 09-Mar-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port
Enable the high-speed UART port connected to the GNSS controller on the
sa8775p-adp development board.
Signed-off-by: Bartosz Golaszewski <
arm64: dts: qcom: sa8775p-ride: enable the GNSS UART port
Enable the high-speed UART port connected to the GNSS controller on the
sa8775p-adp development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-9-brgl@bgdev.pl
show more ...
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| #
a3b31b0e |
| 09-Mar-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: enable the SPI node
Enable the SPI interface exposed on the sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Revie
arm64: dts: qcom: sa8775p-ride: enable the SPI node
Enable the SPI interface exposed on the sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-7-brgl@bgdev.pl
show more ...
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| #
12f35f74 |
| 09-Mar-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: enable i2c18
This enables the I2C interface on the sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: K
arm64: dts: qcom: sa8775p-ride: enable i2c18
This enables the I2C interface on the sa8775p-ride development board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-5-brgl@bgdev.pl
show more ...
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| #
4926a8e9 |
| 09-Mar-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2
Enable the second instance of the QUPv3 engine on the sa8775p-ride board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewe
arm64: dts: qcom: sa8775p-ride: enable QUPv3 #2
Enable the second instance of the QUPv3 engine on the sa8775p-ride board.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230309103752.173541-3-brgl@bgdev.pl
show more ...
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|
Revision tags: v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12 |
|
| #
603f96d4 |
| 14-Feb-2023 |
Bartosz Golaszewski <bartosz.golaszewski@linaro.org> |
arm64: dts: qcom: add initial support for qcom sa8775p-ride
This adds basic support for the Qualcomm sa8775p platform and the
reference board: sa8775p-ride. The dt files describe the basics of the
S
arm64: dts: qcom: add initial support for qcom sa8775p-ride
This adds basic support for the Qualcomm sa8775p platform and the
reference board: sa8775p-ride. The dt files describe the basics of the
SoC and enable booting to shell.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230214092713.211054-3-brgl@bgdev.pl
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