Revision tags: v6.6.25, v6.6.24, v6.6.23, v6.6.16, v6.6.15, v6.6.14, v6.6.13, v6.6.12, v6.6.11, v6.6.10, v6.6.9, v6.6.8, v6.6.7, v6.6.6, v6.6.5, v6.6.4, v6.6.3, v6.6.2, v6.5.11, v6.6.1, v6.5.10, v6.6, v6.5.9, v6.5.8, v6.5.7, v6.5.6, v6.5.5, v6.5.4, v6.5.3, v6.5.2, v6.1.51, v6.5.1, v6.1.50, v6.5, v6.1.49, v6.1.48, v6.1.46, v6.1.45, v6.1.44, v6.1.43, v6.1.42, v6.1.41, v6.1.40, v6.1.39, v6.1.38, v6.1.37, v6.1.36, v6.4, v6.1.35, v6.1.34, v6.1.33, v6.1.32, v6.1.31, v6.1.30, v6.1.29, v6.1.28, v6.1.27, v6.1.26, v6.3 |
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#
a0936e9e |
| 21-Apr-2023 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: hisilicon: add missing cache properties
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like:
hi3660-hikey960.dtb: l2-cache0: 'cac
arm64: dts: hisilicon: add missing cache properties
As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like:
hi3660-hikey960.dtb: l2-cache0: 'cache-unified' is a required property
Link: https://lore.kernel.org/r/20230421223215.115666-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Revision tags: v6.1.25, v6.1.24, v6.1.23, v6.1.22, v6.1.21, v6.1.20, v6.1.19, v6.1.18, v6.1.17, v6.1.16, v6.1.15, v6.1.14, v6.1.13, v6.2, v6.1.12, v6.1.11, v6.1.10, v6.1.9, v6.1.8, v6.1.7, v6.1.6, v6.1.5, v6.0.19, v6.0.18, v6.1.4, v6.1.3, v6.0.17, v6.1.2, v6.0.16, v6.1.1, v6.0.15, v6.0.14, v6.0.13, v6.1, v6.0.12, v6.0.11, v6.0.10, v5.15.80, v6.0.9, v5.15.79, v6.0.8, v5.15.78 |
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#
0de459a3 |
| 07-Nov-2022 |
Pierre Gondois <pierre.gondois@arm.com> |
arm64: dts: Update cache properties for hisilicon
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and S
arm64: dts: Update cache properties for hisilicon
The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Revision tags: v6.0.7, v5.15.77, v5.15.76, v6.0.6, v6.0.5, v5.15.75, v6.0.4, v6.0.3, v6.0.2, v5.15.74, v5.15.73, v6.0.1, v5.15.72, v6.0, v5.15.71, v5.15.70, v5.15.69, v5.15.68, v5.15.67, v5.15.66, v5.15.65, v5.15.64, v5.15.63, v5.15.62, v5.15.61, v5.15.60, v5.15.59, v5.19, v5.15.58, v5.15.57, v5.15.56, v5.15.55, v5.15.54, v5.15.53, v5.15.52, v5.15.51, v5.15.50, v5.15.49, v5.15.48, v5.15.47, v5.15.46, v5.15.45, v5.15.44 |
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#
11357f10 |
| 26-May-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: hisilicon: adjust whitespace around '='
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (s
arm64: dts: hisilicon: adjust whitespace around '='
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220526204453.832681-1-krzysztof.kozlowski@linaro.org
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Revision tags: v5.15.43, v5.15.42, v5.18, v5.15.41, v5.15.40, v5.15.39, v5.15.38, v5.15.37, v5.15.36, v5.15.35 |
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#
65b96377 |
| 19-Apr-2022 |
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> |
arm64: dts: hisilicon: align 'freq-table-hz' with dtschema in UFS
The DT schema expects 'freq-table-hz' property to be an uint32-matrix, which is also easier to read.
Signed-off-by: Krzysztof Kozlo
arm64: dts: hisilicon: align 'freq-table-hz' with dtschema in UFS
The DT schema expects 'freq-table-hz' property to be an uint32-matrix, which is also easier to read.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220306111125.116455-10-krzysztof.kozlowski@canonical.com
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Revision tags: v5.15.34, v5.15.33, v5.15.32, v5.15.31, v5.17, v5.15.30, v5.15.29, v5.15.28, v5.15.27, v5.15.26, v5.15.25, v5.15.24, v5.15.23, v5.15.22, v5.15.21, v5.15.20, v5.15.19, v5.15.18, v5.15.17, v5.4.173, v5.15.16, v5.15.15, v5.16, v5.15.10, v5.15.9, v5.15.8, v5.15.7, v5.15.6, v5.15.5, v5.15.4, v5.15.3, v5.15.2, v5.15.1, v5.15, v5.14.14, v5.14.13, v5.14.12, v5.14.11, v5.14.10, v5.14.9, v5.14.8, v5.14.7, v5.14.6, v5.10.67, v5.10.66, v5.14.5, v5.14.4, v5.10.65, v5.14.3, v5.10.64, v5.14.2, v5.10.63, v5.14.1, v5.10.62, v5.14, v5.10.61 |
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#
dcc3f565 |
| 20-Aug-2021 |
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> |
arm64: dts: hisilicon: align operating-points table name with dtschema
Align the name of operating-points node to dtschema to fix warnings like:
cpu_opp_table: $nodename:0: 'cpu_opp_table' does n
arm64: dts: hisilicon: align operating-points table name with dtschema
Align the name of operating-points node to dtschema to fix warnings like:
cpu_opp_table: $nodename:0: 'cpu_opp_table' does not match '^opp-table(-[a-z0-9]+)?$'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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#
894d4f1f |
| 30-Aug-2021 |
Michael Walle <michael@walle.cc> |
arm64: dts: hisilicon: fix arm,sp805 compatible string
According to Documentation/devicetree/bindings/watchdog/arm,sp805.yaml the compatible is: compatible = "arm,sp805", "arm,primecell";
The cur
arm64: dts: hisilicon: fix arm,sp805 compatible string
According to Documentation/devicetree/bindings/watchdog/arm,sp805.yaml the compatible is: compatible = "arm,sp805", "arm,primecell";
The current compatible string doesn't exist at all. Fix it.
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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#
bed5a80f |
| 30-Aug-2021 |
Michael Walle <michael@walle.cc> |
arm64: dts: hisilicon: fix arm,sp805 compatible string
[ Upstream commit 894d4f1f77d0e88f1f81af2e1e37333c1c41b631 ]
According to Documentation/devicetree/bindings/watchdog/arm,sp805.yaml the compat
arm64: dts: hisilicon: fix arm,sp805 compatible string
[ Upstream commit 894d4f1f77d0e88f1f81af2e1e37333c1c41b631 ]
According to Documentation/devicetree/bindings/watchdog/arm,sp805.yaml the compatible is: compatible = "arm,sp805", "arm,primecell";
The current compatible string doesn't exist at all. Fix it.
Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
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Revision tags: v5.10.60 |
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#
2dc30eb9 |
| 11-Aug-2021 |
Mauro Carvalho Chehab <mchehab+huawei@kernel.org> |
arm64: dts: HiSilicon: hi3660: address a PCI warning
When the driver is registered, it produces a warning when registering the PCI bridge:
[ 5.363450] pci_bus 0000:00: root bus resource [bus 00
arm64: dts: HiSilicon: hi3660: address a PCI warning
When the driver is registered, it produces a warning when registering the PCI bridge:
[ 5.363450] pci_bus 0000:00: root bus resource [bus 00-01] [ 5.396998] pci_bus 0000:01: busn_res: can not insert [bus 01-ff] under [bus 00-01] (conflicts with (null) [bus 00-01]) [ 5.284831] pci 0000:00:00.0: PCI bridge to [bus 01-ff]
The reason is that the bus-range is wrong. Address it.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Revision tags: v5.10.53, v5.10.52, v5.10.51, v5.10.50, v5.10.49, v5.13, v5.10.46, v5.10.43, v5.10.42, v5.10.41, v5.10.40 |
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#
e3211e41 |
| 22-May-2021 |
Hao Fang <fanghao11@huawei.com> |
arm64: dts: hisilicon: use the correct HiSilicon copyright
s/Hisilicon/HiSilicon/. It should use capital S, according to the official website https://www.hisilicon.com/en.
Signed-off-by: Hao Fang <
arm64: dts: hisilicon: use the correct HiSilicon copyright
s/Hisilicon/HiSilicon/. It should use capital S, according to the official website https://www.hisilicon.com/en.
Signed-off-by: Hao Fang <fanghao11@huawei.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Revision tags: v5.10.39, v5.4.119, v5.10.36, v5.10.35, v5.10.34, v5.4.116, v5.10.33, v5.12, v5.10.32, v5.10.31, v5.10.30, v5.10.27, v5.10.26, v5.10.25, v5.10.24, v5.10.23, v5.10.22, v5.10.21, v5.10.20, v5.10.19, v5.4.101, v5.10.18, v5.10.17, v5.11, v5.10.16, v5.10.15, v5.10.14 |
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#
dbbf5131 |
| 17-Jan-2021 |
Zhen Lei <thunder.leizhen@huawei.com> |
arm64: dts: hisilicon: normalize the node name of the module thermal
1. Change the node name of the thermal zone to match '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', add suffix "-thermal". 2. Change t
arm64: dts: hisilicon: normalize the node name of the module thermal
1. Change the node name of the thermal zone to match '^[a-zA-Z][a-zA-Z0-9\\-]{1,12}-thermal$', add suffix "-thermal". 2. Change the node name of the trip point to match '^[a-zA-Z][a-zA-Z0-9\\-_]{0,63}$', delete character "@".
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Revision tags: v5.10 |
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#
4dc5288f |
| 11-Nov-2020 |
Serge Semin <Sergey.Semin@baikalelectronics.ru> |
arm64: dts: hi3660: Harmonize DWC USB3 DT nodes name
In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the
arm64: dts: hi3660: Harmonize DWC USB3 DT nodes name
In accordance with the DWC USB3 bindings the corresponding node name is suppose to comply with the Generic USB HCD DT schema, which requires the USB nodes to have the name acceptable by the regexp: "^usb(@.*)?" . Make sure the "snps,dwc3"-compatible nodes are correctly named.
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Revision tags: v5.8.17, v5.8.16, v5.8.15 |
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#
c85731ab |
| 12-Oct-2020 |
Zhen Lei <thunder.leizhen@huawei.com> |
arm64: dts: hisilicon: list all clocks required by spi-pl022.yaml
The arm,pl022 binding need to specify two clocks: "sspclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver pre
arm64: dts: hisilicon: list all clocks required by spi-pl022.yaml
The arm,pl022 binding need to specify two clocks: "sspclk", "apb_pclk". But only "apb_pclk" is specified now. Because the driver preferentially matches the first clock. Otherwise, it matches the second clock instead of both clocks. So both of them use the same clock don't change the function.
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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#
8c563f55 |
| 12-Oct-2020 |
Zhen Lei <thunder.leizhen@huawei.com> |
arm64: dts: hisilicon: write the values of property-units into a uint32 array
Use <> to separate the values of property-units will be treated as multiple arrays. The errors similar to the following
arm64: dts: hisilicon: write the values of property-units into a uint32 array
Use <> to separate the values of property-units will be treated as multiple arrays. The errors similar to the following will be reported by property-units.yaml.
ufs@ff3c0000: freq-table-hz: [[0, 0], [0, 0]] is too long
Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Revision tags: v5.9, v5.8.14, v5.8.13, v5.8.12, v5.8.11, v5.8.10, v5.8.9, v5.8.8 |
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#
a665b2c1 |
| 07-Sep-2020 |
Andre Przywara <andre.przywara@arm.com> |
arm64: dts: hisilicon: Fix SP805 clocks
The SP805 DT binding requires two clocks to be specified, but Hisilicon platform DTs currently only specify one clock.
In practice, Linux would pick a clock
arm64: dts: hisilicon: Fix SP805 clocks
The SP805 DT binding requires two clocks to be specified, but Hisilicon platform DTs currently only specify one clock.
In practice, Linux would pick a clock named "apb_pclk" for the bus clock, and the Linux and U-Boot SP805 driver would use the first clock to derive the actual watchdog counter frequency.
Since currently both are the very same clock, we can just double the clock reference, and add the correct clock-names, to match the binding.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Revision tags: v5.8.7, v5.8.6, v5.4.62, v5.8.5, v5.8.4, v5.4.61, v5.8.3, v5.4.60, v5.8.2, v5.4.59, v5.8.1, v5.4.58, v5.4.57, v5.4.56, v5.8, v5.7.12, v5.4.55, v5.7.11, v5.4.54, v5.7.10, v5.4.53, v5.4.52, v5.7.9, v5.7.8, v5.4.51 |
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#
47e2843f |
| 03-Jul-2020 |
John Stultz <john.stultz@linaro.org> |
dts: hi3660: Add support for basic usb gadget on Hikey960
This patch adds basic core dwc3, usb phy and rt1711h nodes for usb support on Hikey960.
This does not enable the mux/hub functionality on t
dts: hi3660: Add support for basic usb gadget on Hikey960
This patch adds basic core dwc3, usb phy and rt1711h nodes for usb support on Hikey960.
This does not enable the mux/hub functionality on the board, so the USB-A host ports will not function, but does allow the USB-C port to function in gadget mode (unfortunately not in host, as the hub/mux functionality is needed to enable vbus output to power devices in host mode).
This is based on an old patch originally by Yu Chen.
Cc: Yu Chen <chenyu56@huawei.com> Cc: Chunfeng Yun <chunfeng.yun@mediatek.com> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Binghui Wang <wangbinghui@hisilicon.com> Cc: YongQin Liu <yongqin.liu@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Revision tags: v5.4.50, v5.7.7, v5.4.49, v5.7.6, v5.7.5, v5.4.48, v5.7.4, v5.7.3, v5.4.47, v5.4.46, v5.7.2, v5.4.45, v5.7.1, v5.4.44, v5.7, v5.4.43, v5.4.42, v5.4.41, v5.4.40, v5.4.39, v5.4.38, v5.4.37, v5.4.36, v5.4.35, v5.4.34, v5.4.33, v5.4.32, v5.4.31, v5.4.30, v5.4.29, v5.6, v5.4.28 |
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#
a8dad3e1 |
| 24-Mar-2020 |
Loic Poulain <loic.poulain@linaro.org> |
arm64: dts: hikey960: pinctrl: Fix spi2/spi3 pinconf
Only the pinmux was selected, not the pinconf, leading to spi issues. Increase drive strength so that max speed (25Mhz) can be achieved.
Signed-
arm64: dts: hikey960: pinctrl: Fix spi2/spi3 pinconf
Only the pinmux was selected, not the pinconf, leading to spi issues. Increase drive strength so that max speed (25Mhz) can be achieved.
Signed-off-by: Loic Poulain <loic.poulain@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Revision tags: v5.4.27, v5.4.26, v5.4.25, v5.4.24, v5.4.23, v5.4.22, v5.4.21, v5.4.20, v5.4.19, v5.4.18, v5.4.17, v5.4.16, v5.5, v5.4.15, v5.4.14, v5.4.13, v5.4.12, v5.4.11, v5.4.10, v5.4.9, v5.4.8, v5.4.7, v5.4.6, v5.4.5, v5.4.4, v5.4.3, v5.3.15, v5.4.2, v5.4.1, v5.3.14, v5.4, v5.3.13, v5.3.12, v5.3.11, v5.3.10, v5.3.9, v5.3.8, v5.3.7, v5.3.6, v5.3.5, v5.3.4, v5.3.3, v5.3.2, v5.3.1, v5.3, v5.2.14, v5.3-rc8, v5.2.13, v5.2.12, v5.2.11, v5.2.10, v5.2.9, v5.2.8, v5.2.7, v5.2.6, v5.2.5, v5.2.4, v5.2.3, v5.2.2, v5.2.1, v5.2, v5.1.16, v5.1.15, v5.1.14, v5.1.13, v5.1.12, v5.1.11, v5.1.10, v5.1.9, v5.1.8, v5.1.7, v5.1.6, v5.1.5, v5.1.4, v5.1.3, v5.1.2, v5.1.1, v5.0.14, v5.1, v5.0.13, v5.0.12, v5.0.11, v5.0.10 |
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#
9500ff14 |
| 20-Apr-2019 |
Wanglai Shi <shiwanglai@hisilicon.com> |
arm64: dts: hi3660: Add CoreSight support
This patch adds DT bindings for the CoreSight trace components on hi3660, which is used by 96boards Hikey960.
Signed-off-by: Wanglai Shi <shiwanglai@hisili
arm64: dts: hi3660: Add CoreSight support
This patch adds DT bindings for the CoreSight trace components on hi3660, which is used by 96boards Hikey960.
Signed-off-by: Wanglai Shi <shiwanglai@hisilicon.com> Reviewed-and-tested-by: Leo Yan <leo.yan@linaro.org> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Revision tags: v5.0.9, v5.0.8, v5.0.7 |
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#
6d09e003 |
| 04-Apr-2019 |
John Stultz <john.stultz@linaro.org> |
arm64: dts: hi3660: Fixup unofficial dma-min-chan to dma-channel-mask
A undocumented and unimplemented binding got into the hi3660 dtsi, and this switches that binding to the now documented one.
Cc
arm64: dts: hi3660: Fixup unofficial dma-min-chan to dma-channel-mask
A undocumented and unimplemented binding got into the hi3660 dtsi, and this switches that binding to the now documented one.
Cc: Tanglei Han <hantanglei@huawei.com> Cc: Zhuangluan Su <suzhuangluan@hisilicon.com> Cc: Ryan Grachek <ryan@edited.us> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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#
c9726326 |
| 04-Apr-2019 |
Youlin Wang <wwx575822@notesmail.huawei.com> |
arm64: dts: hi3660: Add hisi asp dma device
Add asp-dma device to hi3660 dts
Cc: Tanglei Han <hantanglei@huawei.com> Cc: Zhuangluan Su <suzhuangluan@hisilicon.com> Cc: Ryan Grachek <ryan@edited.us>
arm64: dts: hi3660: Add hisi asp dma device
Add asp-dma device to hi3660 dts
Cc: Tanglei Han <hantanglei@huawei.com> Cc: Zhuangluan Su <suzhuangluan@hisilicon.com> Cc: Ryan Grachek <ryan@edited.us> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Youlin Wang <wwx575822@notesmail.huawei.com> Signed-off-by: Tanglei Han <hantanglei@huawei.com> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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792cea3f |
| 04-Apr-2019 |
John Stultz <john.stultz@linaro.org> |
arm64: dts: hi3660: Add dma to uart nodes
Try to add DMA support to the uart nodes following the assignments made in the dts from the victoria vendor kernel here: https://consumer.huawei.com/en/open
arm64: dts: hi3660: Add dma to uart nodes
Try to add DMA support to the uart nodes following the assignments made in the dts from the victoria vendor kernel here: https://consumer.huawei.com/en/opensource/detail/?siteCode=worldwide&keywords=p10&fileType=openSourceSoftware&pageSize=10&curPage=1
Cc: Tanglei Han <hantanglei@huawei.com> Cc: Zhuangluan Su <suzhuangluan@hisilicon.com> Cc: Ryan Grachek <ryan@edited.us> Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Revision tags: v5.0.6, v5.0.5, v5.0.4, v5.0.3, v4.19.29, v5.0.2, v4.19.28, v5.0.1, v4.19.27, v5.0, v4.19.26, v4.19.25, v4.19.24, v4.19.23, v4.19.22, v4.19.21, v4.19.20, v4.19.19, v4.19.18, v4.19.17, v4.19.16 |
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31af04cd |
| 14-Jan-2019 |
Rob Herring <robh@kernel.org> |
arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string
The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fal
arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string
The 'arm,armv8' compatible string is only for software models. It adds little value otherwise and is inconsistently used as a fallback on some platforms. Remove it from those platforms.
This fixes warnings generated by the DT schema.
Reported-by: Michal Simek <michal.simek@xilinx.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Will Deacon <will.deacon@arm.com> Acked-by: Antoine Tenart <antoine.tenart@bootlin.com> Acked-by: Nishanth Menon <nm@ti.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Chanho Min <chanho.min@lge.com> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Acked-by: Thierry Reding <treding@nvidia.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Tero Kristo <t-kristo@ti.com> Acked-by: Wei Xu <xuwei5@hisilicon.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Scott Branden <scott.branden@broadcom.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> Acked-by: Robert Richter <rrichter@cavium.com> Acked-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Revision tags: v4.19.15, v4.19.14, v4.19.13, v4.19.12, v4.19.11, v4.19.10, v4.19.9, v4.19.8, v4.19.7, v4.19.6, v4.19.5, v4.19.4, v4.18.20, v4.19.3 |
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6ad5506e |
| 16-Nov-2018 |
Viresh Kumar <viresh.kumar@linaro.org> |
ARM64: dts: hisilicon: Add all CPUs in cooling maps
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Thi
ARM64: dts: hisilicon: Add all CPUs in cooling maps
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures.
Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations.
Update cooling maps to include all devices affected by individual trip points.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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a7a6e2cb |
| 16-Nov-2018 |
Viresh Kumar <viresh.kumar@linaro.org> |
arm64: dts: hi3660: Add missing cooling device properties for CPUs
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of
arm64: dts: hi3660: Add missing cooling device properties for CPUs
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device.
Add such missing properties.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Revision tags: v4.18.19, v4.19.2, v4.18.18, v4.18.17, v4.19.1, v4.19, v4.18.16, v4.18.15, v4.18.14, v4.18.13, v4.18.12, v4.18.11, v4.18.10, v4.18.9, v4.18.7, v4.18.6, v4.18.5, v4.17.18, v4.18.4, v4.18.3, v4.17.17, v4.18.2, v4.17.16, v4.17.15, v4.18.1, v4.18, v4.17.14, v4.17.13, v4.17.12, v4.17.11, v4.17.10, v4.17.9, v4.17.8, v4.17.7, v4.17.6 |
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a5956def |
| 11-Jul-2018 |
Vincent Guittot <vincent.guittot@linaro.org> |
arm64: hikey960: update idle-states
Update entry/exit latency and residency time of hikey960 to use more realistic figures based on unitary tests done on the platform.
The complete results (in us)
arm64: hikey960: update idle-states
Update entry/exit latency and residency time of hikey960 to use more realistic figures based on unitary tests done on the platform.
The complete results (in us) : big cluster cluster CPU max entry latency 800 400 max exit latency 2900 550 residency 903Mhz 5000 1500 residency 2363Mhz 0 1500
little cluster cluster CPU max entry latency 500 400 max exit latency 1600 650 residency 533Mhz 8000 4500 residency 1844Mhz 0 1500
We can see that the residency time depends of the running OPP which is not handled for now. Then we also have to take into account the constraint of a residency time shorter than the tick to get full advantage of idle loop reordering(tick is stopped if idle duration is higher than tick period). Finally the selected residency value are : big cluster cluster CPU residency 3700 1500
little cluster cluster CPU residency 3500 1500
A simple test with a task waking up every 11.111ms shows improvement: - 5% a lowest OPP - 22% at highest OPP
The period has been chosen: - to be shorter than old cluster residency time and longer than new residency time of cluster off C-state - to prevent any sync with tick (4ms) when running tests that can add some variances between tests
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Revision tags: v4.17.5, v4.17.4, v4.17.3 |
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f0ab786f |
| 18-Jun-2018 |
oscardagrach <ryan@edited.us> |
arm64: dts: hikey960: Clean up MMC properties and move to proper file
Certain properties should be moved to the board file to reflect the specific properties of the board, and not the SoC. Move thes
arm64: dts: hikey960: Clean up MMC properties and move to proper file
Certain properties should be moved to the board file to reflect the specific properties of the board, and not the SoC. Move these properties to proper location and organize properties in both files.
Signed-off-by: Ryan Grachek <ryan@edited.us> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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