1// SPDX-License-Identifier: GPL-2.0 2/* 3 * dts file for Hisilicon Hi3660 SoC 4 * 5 * Copyright (C) 2016, Hisilicon Ltd. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/hi3660-clock.h> 10#include <dt-bindings/thermal/thermal.h> 11 12/ { 13 compatible = "hisilicon,hi3660"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 psci { 19 compatible = "arm,psci-0.2"; 20 method = "smc"; 21 }; 22 23 cpus { 24 #address-cells = <2>; 25 #size-cells = <0>; 26 27 cpu-map { 28 cluster0 { 29 core0 { 30 cpu = <&cpu0>; 31 }; 32 core1 { 33 cpu = <&cpu1>; 34 }; 35 core2 { 36 cpu = <&cpu2>; 37 }; 38 core3 { 39 cpu = <&cpu3>; 40 }; 41 }; 42 cluster1 { 43 core0 { 44 cpu = <&cpu4>; 45 }; 46 core1 { 47 cpu = <&cpu5>; 48 }; 49 core2 { 50 cpu = <&cpu6>; 51 }; 52 core3 { 53 cpu = <&cpu7>; 54 }; 55 }; 56 }; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a53"; 60 device_type = "cpu"; 61 reg = <0x0 0x0>; 62 enable-method = "psci"; 63 next-level-cache = <&A53_L2>; 64 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 65 capacity-dmips-mhz = <592>; 66 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 67 operating-points-v2 = <&cluster0_opp>; 68 #cooling-cells = <2>; 69 dynamic-power-coefficient = <110>; 70 }; 71 72 cpu1: cpu@1 { 73 compatible = "arm,cortex-a53"; 74 device_type = "cpu"; 75 reg = <0x0 0x1>; 76 enable-method = "psci"; 77 next-level-cache = <&A53_L2>; 78 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 79 capacity-dmips-mhz = <592>; 80 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 81 operating-points-v2 = <&cluster0_opp>; 82 #cooling-cells = <2>; 83 }; 84 85 cpu2: cpu@2 { 86 compatible = "arm,cortex-a53"; 87 device_type = "cpu"; 88 reg = <0x0 0x2>; 89 enable-method = "psci"; 90 next-level-cache = <&A53_L2>; 91 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 92 capacity-dmips-mhz = <592>; 93 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 94 operating-points-v2 = <&cluster0_opp>; 95 #cooling-cells = <2>; 96 }; 97 98 cpu3: cpu@3 { 99 compatible = "arm,cortex-a53"; 100 device_type = "cpu"; 101 reg = <0x0 0x3>; 102 enable-method = "psci"; 103 next-level-cache = <&A53_L2>; 104 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 105 capacity-dmips-mhz = <592>; 106 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER0>; 107 operating-points-v2 = <&cluster0_opp>; 108 #cooling-cells = <2>; 109 }; 110 111 cpu4: cpu@100 { 112 compatible = "arm,cortex-a73"; 113 device_type = "cpu"; 114 reg = <0x0 0x100>; 115 enable-method = "psci"; 116 next-level-cache = <&A73_L2>; 117 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 118 capacity-dmips-mhz = <1024>; 119 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 120 operating-points-v2 = <&cluster1_opp>; 121 #cooling-cells = <2>; 122 dynamic-power-coefficient = <550>; 123 }; 124 125 cpu5: cpu@101 { 126 compatible = "arm,cortex-a73"; 127 device_type = "cpu"; 128 reg = <0x0 0x101>; 129 enable-method = "psci"; 130 next-level-cache = <&A73_L2>; 131 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 132 capacity-dmips-mhz = <1024>; 133 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 134 operating-points-v2 = <&cluster1_opp>; 135 #cooling-cells = <2>; 136 }; 137 138 cpu6: cpu@102 { 139 compatible = "arm,cortex-a73"; 140 device_type = "cpu"; 141 reg = <0x0 0x102>; 142 enable-method = "psci"; 143 next-level-cache = <&A73_L2>; 144 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 145 capacity-dmips-mhz = <1024>; 146 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 147 operating-points-v2 = <&cluster1_opp>; 148 #cooling-cells = <2>; 149 }; 150 151 cpu7: cpu@103 { 152 compatible = "arm,cortex-a73"; 153 device_type = "cpu"; 154 reg = <0x0 0x103>; 155 enable-method = "psci"; 156 next-level-cache = <&A73_L2>; 157 cpu-idle-states = <&CPU_SLEEP_1 &CLUSTER_SLEEP_1>; 158 capacity-dmips-mhz = <1024>; 159 clocks = <&stub_clock HI3660_CLK_STUB_CLUSTER1>; 160 operating-points-v2 = <&cluster1_opp>; 161 #cooling-cells = <2>; 162 }; 163 164 idle-states { 165 entry-method = "psci"; 166 167 CPU_SLEEP_0: cpu-sleep-0 { 168 compatible = "arm,idle-state"; 169 local-timer-stop; 170 arm,psci-suspend-param = <0x0010000>; 171 entry-latency-us = <400>; 172 exit-latency-us = <650>; 173 min-residency-us = <1500>; 174 }; 175 CLUSTER_SLEEP_0: cluster-sleep-0 { 176 compatible = "arm,idle-state"; 177 local-timer-stop; 178 arm,psci-suspend-param = <0x1010000>; 179 entry-latency-us = <500>; 180 exit-latency-us = <1600>; 181 min-residency-us = <3500>; 182 }; 183 184 185 CPU_SLEEP_1: cpu-sleep-1 { 186 compatible = "arm,idle-state"; 187 local-timer-stop; 188 arm,psci-suspend-param = <0x0010000>; 189 entry-latency-us = <400>; 190 exit-latency-us = <550>; 191 min-residency-us = <1500>; 192 }; 193 194 CLUSTER_SLEEP_1: cluster-sleep-1 { 195 compatible = "arm,idle-state"; 196 local-timer-stop; 197 arm,psci-suspend-param = <0x1010000>; 198 entry-latency-us = <800>; 199 exit-latency-us = <2900>; 200 min-residency-us = <3500>; 201 }; 202 }; 203 204 A53_L2: l2-cache0 { 205 compatible = "cache"; 206 }; 207 208 A73_L2: l2-cache1 { 209 compatible = "cache"; 210 }; 211 }; 212 213 cluster0_opp: opp_table0 { 214 compatible = "operating-points-v2"; 215 opp-shared; 216 217 opp00 { 218 opp-hz = /bits/ 64 <533000000>; 219 opp-microvolt = <700000>; 220 clock-latency-ns = <300000>; 221 }; 222 223 opp01 { 224 opp-hz = /bits/ 64 <999000000>; 225 opp-microvolt = <800000>; 226 clock-latency-ns = <300000>; 227 }; 228 229 opp02 { 230 opp-hz = /bits/ 64 <1402000000>; 231 opp-microvolt = <900000>; 232 clock-latency-ns = <300000>; 233 }; 234 235 opp03 { 236 opp-hz = /bits/ 64 <1709000000>; 237 opp-microvolt = <1000000>; 238 clock-latency-ns = <300000>; 239 }; 240 241 opp04 { 242 opp-hz = /bits/ 64 <1844000000>; 243 opp-microvolt = <1100000>; 244 clock-latency-ns = <300000>; 245 }; 246 }; 247 248 cluster1_opp: opp_table1 { 249 compatible = "operating-points-v2"; 250 opp-shared; 251 252 opp10 { 253 opp-hz = /bits/ 64 <903000000>; 254 opp-microvolt = <700000>; 255 clock-latency-ns = <300000>; 256 }; 257 258 opp11 { 259 opp-hz = /bits/ 64 <1421000000>; 260 opp-microvolt = <800000>; 261 clock-latency-ns = <300000>; 262 }; 263 264 opp12 { 265 opp-hz = /bits/ 64 <1805000000>; 266 opp-microvolt = <900000>; 267 clock-latency-ns = <300000>; 268 }; 269 270 opp13 { 271 opp-hz = /bits/ 64 <2112000000>; 272 opp-microvolt = <1000000>; 273 clock-latency-ns = <300000>; 274 }; 275 276 opp14 { 277 opp-hz = /bits/ 64 <2362000000>; 278 opp-microvolt = <1100000>; 279 clock-latency-ns = <300000>; 280 }; 281 }; 282 283 gic: interrupt-controller@e82b0000 { 284 compatible = "arm,gic-400"; 285 reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 286 <0x0 0xe82b2000 0 0x2000>, /* GICC */ 287 <0x0 0xe82b4000 0 0x2000>, /* GICH */ 288 <0x0 0xe82b6000 0 0x2000>; /* GICV */ 289 #address-cells = <0>; 290 #interrupt-cells = <3>; 291 interrupt-controller; 292 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 293 IRQ_TYPE_LEVEL_HIGH)>; 294 }; 295 296 a53-pmu { 297 compatible = "arm,cortex-a53-pmu"; 298 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 302 interrupt-affinity = <&cpu0>, 303 <&cpu1>, 304 <&cpu2>, 305 <&cpu3>; 306 }; 307 308 a73-pmu { 309 compatible = "arm,cortex-a73-pmu"; 310 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-affinity = <&cpu4>, 315 <&cpu5>, 316 <&cpu6>, 317 <&cpu7>; 318 }; 319 320 timer { 321 compatible = "arm,armv8-timer"; 322 interrupt-parent = <&gic>; 323 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 324 IRQ_TYPE_LEVEL_LOW)>, 325 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 326 IRQ_TYPE_LEVEL_LOW)>, 327 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 328 IRQ_TYPE_LEVEL_LOW)>, 329 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 330 IRQ_TYPE_LEVEL_LOW)>; 331 }; 332 333 soc { 334 compatible = "simple-bus"; 335 #address-cells = <2>; 336 #size-cells = <2>; 337 ranges; 338 339 crg_ctrl: crg_ctrl@fff35000 { 340 compatible = "hisilicon,hi3660-crgctrl", "syscon"; 341 reg = <0x0 0xfff35000 0x0 0x1000>; 342 #clock-cells = <1>; 343 }; 344 345 crg_rst: crg_rst_controller { 346 compatible = "hisilicon,hi3660-reset"; 347 #reset-cells = <2>; 348 hisi,rst-syscon = <&crg_ctrl>; 349 }; 350 351 352 pctrl: pctrl@e8a09000 { 353 compatible = "hisilicon,hi3660-pctrl", "syscon"; 354 reg = <0x0 0xe8a09000 0x0 0x2000>; 355 #clock-cells = <1>; 356 }; 357 358 pmuctrl: crg_ctrl@fff34000 { 359 compatible = "hisilicon,hi3660-pmuctrl", "syscon"; 360 reg = <0x0 0xfff34000 0x0 0x1000>; 361 #clock-cells = <1>; 362 }; 363 364 sctrl: sctrl@fff0a000 { 365 compatible = "hisilicon,hi3660-sctrl", "syscon"; 366 reg = <0x0 0xfff0a000 0x0 0x1000>; 367 #clock-cells = <1>; 368 }; 369 370 iomcu: iomcu@ffd7e000 { 371 compatible = "hisilicon,hi3660-iomcu", "syscon"; 372 reg = <0x0 0xffd7e000 0x0 0x1000>; 373 #clock-cells = <1>; 374 375 }; 376 377 iomcu_rst: reset { 378 compatible = "hisilicon,hi3660-reset"; 379 hisi,rst-syscon = <&iomcu>; 380 #reset-cells = <2>; 381 }; 382 383 mailbox: mailbox@e896b000 { 384 compatible = "hisilicon,hi3660-mbox"; 385 reg = <0x0 0xe896b000 0x0 0x1000>; 386 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 388 #mbox-cells = <3>; 389 }; 390 391 stub_clock: stub_clock@e896b500 { 392 compatible = "hisilicon,hi3660-stub-clk"; 393 reg = <0x0 0xe896b500 0x0 0x0100>; 394 #clock-cells = <1>; 395 mboxes = <&mailbox 13 3 0>; 396 }; 397 398 dual_timer0: timer@fff14000 { 399 compatible = "arm,sp804", "arm,primecell"; 400 reg = <0x0 0xfff14000 0x0 0x1000>; 401 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&crg_ctrl HI3660_OSC32K>, 404 <&crg_ctrl HI3660_OSC32K>, 405 <&crg_ctrl HI3660_OSC32K>; 406 clock-names = "timer1", "timer2", "apb_pclk"; 407 }; 408 409 i2c0: i2c@ffd71000 { 410 compatible = "snps,designware-i2c"; 411 reg = <0x0 0xffd71000 0x0 0x1000>; 412 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 413 #address-cells = <1>; 414 #size-cells = <0>; 415 clock-frequency = <400000>; 416 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C0>; 417 resets = <&iomcu_rst 0x20 3>; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&i2c0_pmx_func &i2c0_cfg_func>; 420 status = "disabled"; 421 }; 422 423 i2c1: i2c@ffd72000 { 424 compatible = "snps,designware-i2c"; 425 reg = <0x0 0xffd72000 0x0 0x1000>; 426 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 clock-frequency = <400000>; 430 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C1>; 431 resets = <&iomcu_rst 0x20 4>; 432 pinctrl-names = "default"; 433 pinctrl-0 = <&i2c1_pmx_func &i2c1_cfg_func>; 434 status = "disabled"; 435 }; 436 437 i2c3: i2c@fdf0c000 { 438 compatible = "snps,designware-i2c"; 439 reg = <0x0 0xfdf0c000 0x0 0x1000>; 440 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 clock-frequency = <400000>; 444 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C3>; 445 resets = <&crg_rst 0x78 7>; 446 pinctrl-names = "default"; 447 pinctrl-0 = <&i2c3_pmx_func &i2c3_cfg_func>; 448 status = "disabled"; 449 }; 450 451 i2c7: i2c@fdf0b000 { 452 compatible = "snps,designware-i2c"; 453 reg = <0x0 0xfdf0b000 0x0 0x1000>; 454 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 clock-frequency = <400000>; 458 clocks = <&crg_ctrl HI3660_CLK_GATE_I2C7>; 459 resets = <&crg_rst 0x60 14>; 460 pinctrl-names = "default"; 461 pinctrl-0 = <&i2c7_pmx_func &i2c7_cfg_func>; 462 status = "disabled"; 463 }; 464 465 uart0: serial@fdf02000 { 466 compatible = "arm,pl011", "arm,primecell"; 467 reg = <0x0 0xfdf02000 0x0 0x1000>; 468 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&crg_ctrl HI3660_CLK_MUX_UART0>, 470 <&crg_ctrl HI3660_PCLK>; 471 clock-names = "uartclk", "apb_pclk"; 472 pinctrl-names = "default"; 473 pinctrl-0 = <&uart0_pmx_func &uart0_cfg_func>; 474 status = "disabled"; 475 }; 476 477 uart1: serial@fdf00000 { 478 compatible = "arm,pl011", "arm,primecell"; 479 reg = <0x0 0xfdf00000 0x0 0x1000>; 480 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 481 dma-names = "rx", "tx"; 482 dmas = <&dma0 2 &dma0 3>; 483 clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, 484 <&crg_ctrl HI3660_CLK_GATE_UART1>; 485 clock-names = "uartclk", "apb_pclk"; 486 pinctrl-names = "default"; 487 pinctrl-0 = <&uart1_pmx_func &uart1_cfg_func>; 488 status = "disabled"; 489 }; 490 491 uart2: serial@fdf03000 { 492 compatible = "arm,pl011", "arm,primecell"; 493 reg = <0x0 0xfdf03000 0x0 0x1000>; 494 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 495 dma-names = "rx", "tx"; 496 dmas = <&dma0 4 &dma0 5>; 497 clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, 498 <&crg_ctrl HI3660_PCLK>; 499 clock-names = "uartclk", "apb_pclk"; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&uart2_pmx_func &uart2_cfg_func>; 502 status = "disabled"; 503 }; 504 505 uart3: serial@ffd74000 { 506 compatible = "arm,pl011", "arm,primecell"; 507 reg = <0x0 0xffd74000 0x0 0x1000>; 508 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&crg_ctrl HI3660_FACTOR_UART3>, 510 <&crg_ctrl HI3660_PCLK>; 511 clock-names = "uartclk", "apb_pclk"; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&uart3_pmx_func &uart3_cfg_func>; 514 status = "disabled"; 515 }; 516 517 uart4: serial@fdf01000 { 518 compatible = "arm,pl011", "arm,primecell"; 519 reg = <0x0 0xfdf01000 0x0 0x1000>; 520 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 521 dma-names = "rx", "tx"; 522 dmas = <&dma0 6 &dma0 7>; 523 clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, 524 <&crg_ctrl HI3660_CLK_GATE_UART4>; 525 clock-names = "uartclk", "apb_pclk"; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&uart4_pmx_func &uart4_cfg_func>; 528 status = "disabled"; 529 }; 530 531 uart5: serial@fdf05000 { 532 compatible = "arm,pl011", "arm,primecell"; 533 reg = <0x0 0xfdf05000 0x0 0x1000>; 534 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 535 dma-names = "rx", "tx"; 536 dmas = <&dma0 8 &dma0 9>; 537 clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, 538 <&crg_ctrl HI3660_CLK_GATE_UART5>; 539 clock-names = "uartclk", "apb_pclk"; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&uart5_pmx_func &uart5_cfg_func>; 542 status = "disabled"; 543 }; 544 545 uart6: serial@fff32000 { 546 compatible = "arm,pl011", "arm,primecell"; 547 reg = <0x0 0xfff32000 0x0 0x1000>; 548 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&crg_ctrl HI3660_CLK_UART6>, 550 <&crg_ctrl HI3660_PCLK>; 551 clock-names = "uartclk", "apb_pclk"; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&uart6_pmx_func &uart6_cfg_func>; 554 status = "disabled"; 555 }; 556 557 dma0: dma@fdf30000 { 558 compatible = "hisilicon,k3-dma-1.0"; 559 reg = <0x0 0xfdf30000 0x0 0x1000>; 560 #dma-cells = <1>; 561 dma-channels = <16>; 562 dma-requests = <32>; 563 dma-min-chan = <1>; 564 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 565 clocks = <&crg_ctrl HI3660_CLK_GATE_DMAC>; 566 dma-no-cci; 567 dma-type = "hi3660_dma"; 568 }; 569 570 rtc0: rtc@fff04000 { 571 compatible = "arm,pl031", "arm,primecell"; 572 reg = <0x0 0Xfff04000 0x0 0x1000>; 573 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&crg_ctrl HI3660_PCLK>; 575 clock-names = "apb_pclk"; 576 }; 577 578 gpio0: gpio@e8a0b000 { 579 compatible = "arm,pl061", "arm,primecell"; 580 reg = <0 0xe8a0b000 0 0x1000>; 581 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 582 gpio-controller; 583 #gpio-cells = <2>; 584 gpio-ranges = <&pmx0 1 0 7>; 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 clocks = <&crg_ctrl HI3660_PCLK_GPIO0>; 588 clock-names = "apb_pclk"; 589 }; 590 591 gpio1: gpio@e8a0c000 { 592 compatible = "arm,pl061", "arm,primecell"; 593 reg = <0 0xe8a0c000 0 0x1000>; 594 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 595 gpio-controller; 596 #gpio-cells = <2>; 597 gpio-ranges = <&pmx0 1 7 7>; 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 clocks = <&crg_ctrl HI3660_PCLK_GPIO1>; 601 clock-names = "apb_pclk"; 602 }; 603 604 gpio2: gpio@e8a0d000 { 605 compatible = "arm,pl061", "arm,primecell"; 606 reg = <0 0xe8a0d000 0 0x1000>; 607 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 608 gpio-controller; 609 #gpio-cells = <2>; 610 gpio-ranges = <&pmx0 0 14 8>; 611 interrupt-controller; 612 #interrupt-cells = <2>; 613 clocks = <&crg_ctrl HI3660_PCLK_GPIO2>; 614 clock-names = "apb_pclk"; 615 }; 616 617 gpio3: gpio@e8a0e000 { 618 compatible = "arm,pl061", "arm,primecell"; 619 reg = <0 0xe8a0e000 0 0x1000>; 620 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 621 gpio-controller; 622 #gpio-cells = <2>; 623 gpio-ranges = <&pmx0 0 22 8>; 624 interrupt-controller; 625 #interrupt-cells = <2>; 626 clocks = <&crg_ctrl HI3660_PCLK_GPIO3>; 627 clock-names = "apb_pclk"; 628 }; 629 630 gpio4: gpio@e8a0f000 { 631 compatible = "arm,pl061", "arm,primecell"; 632 reg = <0 0xe8a0f000 0 0x1000>; 633 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 634 gpio-controller; 635 #gpio-cells = <2>; 636 gpio-ranges = <&pmx0 0 30 8>; 637 interrupt-controller; 638 #interrupt-cells = <2>; 639 clocks = <&crg_ctrl HI3660_PCLK_GPIO4>; 640 clock-names = "apb_pclk"; 641 }; 642 643 gpio5: gpio@e8a10000 { 644 compatible = "arm,pl061", "arm,primecell"; 645 reg = <0 0xe8a10000 0 0x1000>; 646 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 647 gpio-controller; 648 #gpio-cells = <2>; 649 gpio-ranges = <&pmx0 0 38 8>; 650 interrupt-controller; 651 #interrupt-cells = <2>; 652 clocks = <&crg_ctrl HI3660_PCLK_GPIO5>; 653 clock-names = "apb_pclk"; 654 }; 655 656 gpio6: gpio@e8a11000 { 657 compatible = "arm,pl061", "arm,primecell"; 658 reg = <0 0xe8a11000 0 0x1000>; 659 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 660 gpio-controller; 661 #gpio-cells = <2>; 662 gpio-ranges = <&pmx0 0 46 8>; 663 interrupt-controller; 664 #interrupt-cells = <2>; 665 clocks = <&crg_ctrl HI3660_PCLK_GPIO6>; 666 clock-names = "apb_pclk"; 667 }; 668 669 gpio7: gpio@e8a12000 { 670 compatible = "arm,pl061", "arm,primecell"; 671 reg = <0 0xe8a12000 0 0x1000>; 672 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 673 gpio-controller; 674 #gpio-cells = <2>; 675 gpio-ranges = <&pmx0 0 54 8>; 676 interrupt-controller; 677 #interrupt-cells = <2>; 678 clocks = <&crg_ctrl HI3660_PCLK_GPIO7>; 679 clock-names = "apb_pclk"; 680 }; 681 682 gpio8: gpio@e8a13000 { 683 compatible = "arm,pl061", "arm,primecell"; 684 reg = <0 0xe8a13000 0 0x1000>; 685 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 686 gpio-controller; 687 #gpio-cells = <2>; 688 gpio-ranges = <&pmx0 0 62 8>; 689 interrupt-controller; 690 #interrupt-cells = <2>; 691 clocks = <&crg_ctrl HI3660_PCLK_GPIO8>; 692 clock-names = "apb_pclk"; 693 }; 694 695 gpio9: gpio@e8a14000 { 696 compatible = "arm,pl061", "arm,primecell"; 697 reg = <0 0xe8a14000 0 0x1000>; 698 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 699 gpio-controller; 700 #gpio-cells = <2>; 701 gpio-ranges = <&pmx0 0 70 8>; 702 interrupt-controller; 703 #interrupt-cells = <2>; 704 clocks = <&crg_ctrl HI3660_PCLK_GPIO9>; 705 clock-names = "apb_pclk"; 706 }; 707 708 gpio10: gpio@e8a15000 { 709 compatible = "arm,pl061", "arm,primecell"; 710 reg = <0 0xe8a15000 0 0x1000>; 711 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 712 gpio-controller; 713 #gpio-cells = <2>; 714 gpio-ranges = <&pmx0 0 78 8>; 715 interrupt-controller; 716 #interrupt-cells = <2>; 717 clocks = <&crg_ctrl HI3660_PCLK_GPIO10>; 718 clock-names = "apb_pclk"; 719 }; 720 721 gpio11: gpio@e8a16000 { 722 compatible = "arm,pl061", "arm,primecell"; 723 reg = <0 0xe8a16000 0 0x1000>; 724 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 725 gpio-controller; 726 #gpio-cells = <2>; 727 gpio-ranges = <&pmx0 0 86 8>; 728 interrupt-controller; 729 #interrupt-cells = <2>; 730 clocks = <&crg_ctrl HI3660_PCLK_GPIO11>; 731 clock-names = "apb_pclk"; 732 }; 733 734 gpio12: gpio@e8a17000 { 735 compatible = "arm,pl061", "arm,primecell"; 736 reg = <0 0xe8a17000 0 0x1000>; 737 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 738 gpio-controller; 739 #gpio-cells = <2>; 740 gpio-ranges = <&pmx0 0 94 3 &pmx0 7 101 1>; 741 interrupt-controller; 742 #interrupt-cells = <2>; 743 clocks = <&crg_ctrl HI3660_PCLK_GPIO12>; 744 clock-names = "apb_pclk"; 745 }; 746 747 gpio13: gpio@e8a18000 { 748 compatible = "arm,pl061", "arm,primecell"; 749 reg = <0 0xe8a18000 0 0x1000>; 750 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 751 gpio-controller; 752 #gpio-cells = <2>; 753 gpio-ranges = <&pmx0 0 102 8>; 754 interrupt-controller; 755 #interrupt-cells = <2>; 756 clocks = <&crg_ctrl HI3660_PCLK_GPIO13>; 757 clock-names = "apb_pclk"; 758 }; 759 760 gpio14: gpio@e8a19000 { 761 compatible = "arm,pl061", "arm,primecell"; 762 reg = <0 0xe8a19000 0 0x1000>; 763 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 764 gpio-controller; 765 #gpio-cells = <2>; 766 gpio-ranges = <&pmx0 0 110 8>; 767 interrupt-controller; 768 #interrupt-cells = <2>; 769 clocks = <&crg_ctrl HI3660_PCLK_GPIO14>; 770 clock-names = "apb_pclk"; 771 }; 772 773 gpio15: gpio@e8a1a000 { 774 compatible = "arm,pl061", "arm,primecell"; 775 reg = <0 0xe8a1a000 0 0x1000>; 776 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 777 gpio-controller; 778 #gpio-cells = <2>; 779 gpio-ranges = <&pmx0 0 118 6>; 780 interrupt-controller; 781 #interrupt-cells = <2>; 782 clocks = <&crg_ctrl HI3660_PCLK_GPIO15>; 783 clock-names = "apb_pclk"; 784 }; 785 786 gpio16: gpio@e8a1b000 { 787 compatible = "arm,pl061", "arm,primecell"; 788 reg = <0 0xe8a1b000 0 0x1000>; 789 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 790 gpio-controller; 791 #gpio-cells = <2>; 792 interrupt-controller; 793 #interrupt-cells = <2>; 794 clocks = <&crg_ctrl HI3660_PCLK_GPIO16>; 795 clock-names = "apb_pclk"; 796 }; 797 798 gpio17: gpio@e8a1c000 { 799 compatible = "arm,pl061", "arm,primecell"; 800 reg = <0 0xe8a1c000 0 0x1000>; 801 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 802 gpio-controller; 803 #gpio-cells = <2>; 804 interrupt-controller; 805 #interrupt-cells = <2>; 806 clocks = <&crg_ctrl HI3660_PCLK_GPIO17>; 807 clock-names = "apb_pclk"; 808 }; 809 810 gpio18: gpio@ff3b4000 { 811 compatible = "arm,pl061", "arm,primecell"; 812 reg = <0 0xff3b4000 0 0x1000>; 813 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 814 gpio-controller; 815 #gpio-cells = <2>; 816 gpio-ranges = <&pmx2 0 0 8>; 817 interrupt-controller; 818 #interrupt-cells = <2>; 819 clocks = <&crg_ctrl HI3660_PCLK_GPIO18>; 820 clock-names = "apb_pclk"; 821 }; 822 823 gpio19: gpio@ff3b5000 { 824 compatible = "arm,pl061", "arm,primecell"; 825 reg = <0 0xff3b5000 0 0x1000>; 826 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 827 gpio-controller; 828 #gpio-cells = <2>; 829 gpio-ranges = <&pmx2 0 8 4>; 830 interrupt-controller; 831 #interrupt-cells = <2>; 832 clocks = <&crg_ctrl HI3660_PCLK_GPIO19>; 833 clock-names = "apb_pclk"; 834 }; 835 836 gpio20: gpio@e8a1f000 { 837 compatible = "arm,pl061", "arm,primecell"; 838 reg = <0 0xe8a1f000 0 0x1000>; 839 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 840 gpio-controller; 841 #gpio-cells = <2>; 842 gpio-ranges = <&pmx1 0 0 6>; 843 interrupt-controller; 844 #interrupt-cells = <2>; 845 clocks = <&crg_ctrl HI3660_PCLK_GPIO20>; 846 clock-names = "apb_pclk"; 847 }; 848 849 gpio21: gpio@e8a20000 { 850 compatible = "arm,pl061", "arm,primecell"; 851 reg = <0 0xe8a20000 0 0x1000>; 852 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 853 gpio-controller; 854 #gpio-cells = <2>; 855 interrupt-controller; 856 #interrupt-cells = <2>; 857 gpio-ranges = <&pmx3 0 0 6>; 858 clocks = <&crg_ctrl HI3660_PCLK_GPIO21>; 859 clock-names = "apb_pclk"; 860 }; 861 862 gpio22: gpio@fff0b000 { 863 compatible = "arm,pl061", "arm,primecell"; 864 reg = <0 0xfff0b000 0 0x1000>; 865 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 866 gpio-controller; 867 #gpio-cells = <2>; 868 /* GPIO176 */ 869 gpio-ranges = <&pmx4 2 0 6>; 870 interrupt-controller; 871 #interrupt-cells = <2>; 872 clocks = <&sctrl HI3660_PCLK_AO_GPIO0>; 873 clock-names = "apb_pclk"; 874 }; 875 876 gpio23: gpio@fff0c000 { 877 compatible = "arm,pl061", "arm,primecell"; 878 reg = <0 0xfff0c000 0 0x1000>; 879 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 880 gpio-controller; 881 #gpio-cells = <2>; 882 /* GPIO184 */ 883 gpio-ranges = <&pmx4 0 6 7>; 884 interrupt-controller; 885 #interrupt-cells = <2>; 886 clocks = <&sctrl HI3660_PCLK_AO_GPIO1>; 887 clock-names = "apb_pclk"; 888 }; 889 890 gpio24: gpio@fff0d000 { 891 compatible = "arm,pl061", "arm,primecell"; 892 reg = <0 0xfff0d000 0 0x1000>; 893 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 894 gpio-controller; 895 #gpio-cells = <2>; 896 /* GPIO192 */ 897 gpio-ranges = <&pmx4 0 13 8>; 898 interrupt-controller; 899 #interrupt-cells = <2>; 900 clocks = <&sctrl HI3660_PCLK_AO_GPIO2>; 901 clock-names = "apb_pclk"; 902 }; 903 904 gpio25: gpio@fff0e000 { 905 compatible = "arm,pl061", "arm,primecell"; 906 reg = <0 0xfff0e000 0 0x1000>; 907 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 908 gpio-controller; 909 #gpio-cells = <2>; 910 /* GPIO200 */ 911 gpio-ranges = <&pmx4 0 21 4 &pmx4 5 25 3>; 912 interrupt-controller; 913 #interrupt-cells = <2>; 914 clocks = <&sctrl HI3660_PCLK_AO_GPIO3>; 915 clock-names = "apb_pclk"; 916 }; 917 918 gpio26: gpio@fff0f000 { 919 compatible = "arm,pl061", "arm,primecell"; 920 reg = <0 0xfff0f000 0 0x1000>; 921 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 922 gpio-controller; 923 #gpio-cells = <2>; 924 /* GPIO208 */ 925 gpio-ranges = <&pmx4 0 28 8>; 926 interrupt-controller; 927 #interrupt-cells = <2>; 928 clocks = <&sctrl HI3660_PCLK_AO_GPIO4>; 929 clock-names = "apb_pclk"; 930 }; 931 932 gpio27: gpio@fff10000 { 933 compatible = "arm,pl061", "arm,primecell"; 934 reg = <0 0xfff10000 0 0x1000>; 935 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 936 gpio-controller; 937 #gpio-cells = <2>; 938 /* GPIO216 */ 939 gpio-ranges = <&pmx4 0 36 6>; 940 interrupt-controller; 941 #interrupt-cells = <2>; 942 clocks = <&sctrl HI3660_PCLK_AO_GPIO5>; 943 clock-names = "apb_pclk"; 944 }; 945 946 gpio28: gpio@fff1d000 { 947 compatible = "arm,pl061", "arm,primecell"; 948 reg = <0 0xfff1d000 0 0x1000>; 949 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 950 gpio-controller; 951 #gpio-cells = <2>; 952 interrupt-controller; 953 #interrupt-cells = <2>; 954 clocks = <&sctrl HI3660_PCLK_AO_GPIO6>; 955 clock-names = "apb_pclk"; 956 }; 957 958 spi2: spi@ffd68000 { 959 compatible = "arm,pl022", "arm,primecell"; 960 reg = <0x0 0xffd68000 0x0 0x1000>; 961 #address-cells = <1>; 962 #size-cells = <0>; 963 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 964 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>; 965 clock-names = "apb_pclk"; 966 pinctrl-names = "default"; 967 pinctrl-0 = <&spi2_pmx_func>; 968 num-cs = <1>; 969 cs-gpios = <&gpio27 2 0>; 970 status = "disabled"; 971 }; 972 973 spi3: spi@ff3b3000 { 974 compatible = "arm,pl022", "arm,primecell"; 975 reg = <0x0 0xff3b3000 0x0 0x1000>; 976 #address-cells = <1>; 977 #size-cells = <0>; 978 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>; 980 clock-names = "apb_pclk"; 981 pinctrl-names = "default"; 982 pinctrl-0 = <&spi3_pmx_func>; 983 num-cs = <1>; 984 cs-gpios = <&gpio18 5 0>; 985 status = "disabled"; 986 }; 987 988 pcie@f4000000 { 989 compatible = "hisilicon,kirin960-pcie"; 990 reg = <0x0 0xf4000000 0x0 0x1000>, 991 <0x0 0xff3fe000 0x0 0x1000>, 992 <0x0 0xf3f20000 0x0 0x40000>, 993 <0x0 0xf5000000 0x0 0x2000>; 994 reg-names = "dbi", "apb", "phy", "config"; 995 bus-range = <0x0 0x1>; 996 #address-cells = <3>; 997 #size-cells = <2>; 998 device_type = "pci"; 999 ranges = <0x02000000 0x0 0x00000000 1000 0x0 0xf6000000 1001 0x0 0x02000000>; 1002 num-lanes = <1>; 1003 #interrupt-cells = <1>; 1004 interrupts = <0 283 4>; 1005 interrupt-names = "msi"; 1006 interrupt-map-mask = <0xf800 0 0 7>; 1007 interrupt-map = <0x0 0 0 1 1008 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1009 <0x0 0 0 2 1010 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1011 <0x0 0 0 3 1012 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1013 <0x0 0 0 4 1014 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, 1016 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, 1017 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, 1018 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, 1019 <&crg_ctrl HI3660_ACLK_GATE_PCIE>; 1020 clock-names = "pcie_phy_ref", "pcie_aux", 1021 "pcie_apb_phy", "pcie_apb_sys", 1022 "pcie_aclk"; 1023 reset-gpios = <&gpio11 1 0 >; 1024 }; 1025 1026 /* UFS */ 1027 ufs: ufs@ff3b0000 { 1028 compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1"; 1029 /* 0: HCI standard */ 1030 /* 1: UFS SYS CTRL */ 1031 reg = <0x0 0xff3b0000 0x0 0x1000>, 1032 <0x0 0xff3b1000 0x0 0x1000>; 1033 interrupt-parent = <&gic>; 1034 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>, 1036 <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>; 1037 clock-names = "ref_clk", "phy_clk"; 1038 freq-table-hz = <0 0>, <0 0>; 1039 /* offset: 0x84; bit: 12 */ 1040 resets = <&crg_rst 0x84 12>; 1041 reset-names = "rst"; 1042 }; 1043 1044 /* SD */ 1045 dwmmc1: dwmmc1@ff37f000 { 1046 compatible = "hisilicon,hi3660-dw-mshc"; 1047 reg = <0x0 0xff37f000 0x0 0x1000>; 1048 #address-cells = <1>; 1049 #size-cells = <0>; 1050 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&crg_ctrl HI3660_CLK_GATE_SD>, 1052 <&crg_ctrl HI3660_HCLK_GATE_SD>; 1053 clock-names = "ciu", "biu"; 1054 clock-frequency = <3200000>; 1055 resets = <&crg_rst 0x94 18>; 1056 reset-names = "reset"; 1057 hisilicon,peripheral-syscon = <&sctrl>; 1058 card-detect-delay = <200>; 1059 status = "disabled"; 1060 }; 1061 1062 /* SDIO */ 1063 dwmmc2: dwmmc2@ff3ff000 { 1064 compatible = "hisilicon,hi3660-dw-mshc"; 1065 reg = <0x0 0xff3ff000 0x0 0x1000>; 1066 #address-cells = <0x1>; 1067 #size-cells = <0x0>; 1068 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1069 clocks = <&crg_ctrl HI3660_CLK_GATE_SDIO0>, 1070 <&crg_ctrl HI3660_HCLK_GATE_SDIO0>; 1071 clock-names = "ciu", "biu"; 1072 resets = <&crg_rst 0x94 20>; 1073 reset-names = "reset"; 1074 card-detect-delay = <200>; 1075 status = "disabled"; 1076 }; 1077 1078 watchdog0: watchdog@e8a06000 { 1079 compatible = "arm,sp805-wdt", "arm,primecell"; 1080 reg = <0x0 0xe8a06000 0x0 0x1000>; 1081 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1082 clocks = <&crg_ctrl HI3660_OSC32K>; 1083 clock-names = "apb_pclk"; 1084 }; 1085 1086 watchdog1: watchdog@e8a07000 { 1087 compatible = "arm,sp805-wdt", "arm,primecell"; 1088 reg = <0x0 0xe8a07000 0x0 0x1000>; 1089 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1090 clocks = <&crg_ctrl HI3660_OSC32K>; 1091 clock-names = "apb_pclk"; 1092 }; 1093 1094 tsensor: tsensor@fff30000 { 1095 compatible = "hisilicon,hi3660-tsensor"; 1096 reg = <0x0 0xfff30000 0x0 0x1000>; 1097 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1098 #thermal-sensor-cells = <1>; 1099 }; 1100 1101 thermal-zones { 1102 1103 cls0: cls0 { 1104 polling-delay = <1000>; 1105 polling-delay-passive = <100>; 1106 sustainable-power = <4500>; 1107 1108 /* sensor ID */ 1109 thermal-sensors = <&tsensor 1>; 1110 1111 trips { 1112 threshold: trip-point@0 { 1113 temperature = <65000>; 1114 hysteresis = <1000>; 1115 type = "passive"; 1116 }; 1117 1118 target: trip-point@1 { 1119 temperature = <75000>; 1120 hysteresis = <1000>; 1121 type = "passive"; 1122 }; 1123 }; 1124 1125 cooling-maps { 1126 map0 { 1127 trip = <&target>; 1128 contribution = <1024>; 1129 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1130 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1131 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1132 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1133 }; 1134 map1 { 1135 trip = <&target>; 1136 contribution = <512>; 1137 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1138 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1139 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1140 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1141 }; 1142 }; 1143 }; 1144 }; 1145 }; 1146}; 1147