Revision tags: v3.15-rc5, v3.15-rc4, v3.15-rc3, v3.15-rc2, v3.15-rc1, v3.14, v3.14-rc8, v3.14-rc7, v3.14-rc6, v3.14-rc5, v3.14-rc4, v3.14-rc3, v3.14-rc2, v3.14-rc1, v3.13, v3.13-rc8, v3.13-rc7, v3.13-rc6, v3.13-rc5, v3.13-rc4, v3.13-rc3, v3.13-rc2, v3.13-rc1, v3.12, v3.12-rc7, v3.12-rc6, v3.12-rc5, v3.12-rc4, v3.12-rc3, v3.12-rc2, v3.12-rc1, v3.11, v3.11-rc7, v3.11-rc6, v3.11-rc5, v3.11-rc4, v3.11-rc3, v3.11-rc2, v3.11-rc1, v3.10, v3.10-rc7, v3.10-rc6, v3.10-rc5, v3.10-rc4, v3.10-rc3, v3.10-rc2, v3.10-rc1, v3.9, v3.9-rc8, v3.9-rc7, v3.9-rc6, v3.9-rc5, v3.9-rc4, v3.9-rc3, v3.9-rc2, v3.9-rc1, v3.8, v3.8-rc7, v3.8-rc6, v3.8-rc5, v3.8-rc4, v3.8-rc3, v3.8-rc2, v3.8-rc1 |
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3d1ff755 |
| 19-Dec-2012 |
Mark Rutland <mark.rutland@arm.com> |
arm: perf: clean up PMU names
The perf userspace tools can't handle dashes or spaces in PMU names, which conflicts with the current naming scheme in the arm perf backend. This prevents these PMUs fr
arm: perf: clean up PMU names
The perf userspace tools can't handle dashes or spaces in PMU names, which conflicts with the current naming scheme in the arm perf backend. This prevents these PMUs from being accessed by name from the perf tools. Additionally the ARMv6 pmus are named "v6", which does not fully distinguish them in the sys/bus/event_source namespace.
This patch renames the PMUs consistently to a lower case form with underscores, e.g. "armv6_1176", "armv7_cortex_a9". This is both readily accepted by today's perf tool, and far easier to type than the (apparently unused) convention in use previously. The OProfile name conversion code is updated to handle this.
Due to a copy-paste error involving two "xscale1" entries, "xscale2" has never been matched by the name OProfile name mapping. While we're updating names, this is corrected.
Acked-by: Will Deacon <will.deacon@arm.com> Tested-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Mark Rutland <mark.rutland@arm.com> [sachin: fixed missing semicolons in armv6 backend] Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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6b7658ec |
| 30-May-2014 |
Mark Rutland <mark.rutland@arm.com> |
arm: perf: armv7: condense event maps
Now that we have macros for declaring fully invalid event maps, put them to work for all the ARMv7 PMU event maps. While this necessitates repeating common indi
arm: perf: armv7: condense event maps
Now that we have macros for declaring fully invalid event maps, put them to work for all the ARMv7 PMU event maps. While this necessitates repeating common indices, we no longer need to refer to *_UNSUPPORTED events at all, and it makes it possible for the even maps to fit on a single page on a reasonably sized monitor.
Acked-by: Will Deacon <will.deacon@arm.com> Tested-by: Christopher Covington <cov@codeaurora.org> Signed-off-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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6a78371a |
| 19-Jun-2014 |
Russell King <rmk+kernel@arm.linux.org.uk> |
ARM: perf: fix compiler warning with gcc 4.6.4 (and tidy code)
GCC 4.6.4 spits out the following warning when building perf_event_v7.c:
arch/arm/kernel/perf_event_v7.c: In function 'krait_pmu_get_e
ARM: perf: fix compiler warning with gcc 4.6.4 (and tidy code)
GCC 4.6.4 spits out the following warning when building perf_event_v7.c:
arch/arm/kernel/perf_event_v7.c: In function 'krait_pmu_get_event_idx': arch/arm/kernel/perf_event_v7.c:1927:6: warning: 'bit' may be used uninitialized in this function
While upgrading the version of gcc may solve this, the code can also be organised to be more efficient by not carrying more local variables than is necessary across the armv7pmu_get_event_idx function call. If we set 'bit' to -1 (which is invalid for clear_bit) we can use that as an indication whether we need to clear a bit after this function.
Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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03eff46c |
| 09-May-2014 |
Will Deacon <will.deacon@arm.com> |
ARM: 8054/1: perf: add support for the Cortex-A17 PMU
The Cortex-A17 PMU is identical to that of the A12, so wire up a new compatible string to the existing event structures.
Signed-off-by: Will De
ARM: 8054/1: perf: add support for the Cortex-A17 PMU
The Cortex-A17 PMU is identical to that of the A12, so wire up a new compatible string to the existing event structures.
Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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8e781f65 |
| 29-Jan-2014 |
Albin Tonnerre <albin.tonnerre@arm.com> |
ARM: perf: add support for the Cortex-A12 PMU
Cortex-A12 implements Performance Monitors compliant with the PMUv2 architecture.
This patch adds support for the Cortex-A12 PMU to the ARM perf backen
ARM: perf: add support for the Cortex-A12 PMU
Cortex-A12 implements Performance Monitors compliant with the PMUv2 architecture.
This patch adds support for the Cortex-A12 PMU to the ARM perf backend.
Signed-off-by: Albin Tonnerre <albin.tonnerre@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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b7aafe99 |
| 07-Feb-2014 |
Stephen Boyd <sboyd@codeaurora.org> |
ARM: perf: fully support Krait CPU PMU events
Krait supports a set of performance monitor region event selection registers (PMRESR) sitting behind a cp15 based interface that extend the architected
ARM: perf: fully support Krait CPU PMU events
Krait supports a set of performance monitor region event selection registers (PMRESR) sitting behind a cp15 based interface that extend the architected PMU events to include Krait CPU and Venum VFP specific events. To use these events the user is expected to program the region register (PMRESRn) with the event code shifted into the group they care about and then point the PMNx event at that region+group combo by writing a PMRESRn_GROUPx event. Add support for this hardware.
Note: the raw event number is a pure software construct that allows us to map the multi-dimensional number space of regions, groups, and event codes into a flat event number space suitable for use by the perf framework.
This is based on code originally written by Ashwin Chaugule and Neil Leeder [1].
[1] https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/kernel/perf_event_msm_krait.c?h=msm-3.4
Cc: Neil Leeder <nleeder@codeaurora.org> Cc: Ashwin Chaugule <ashwinc@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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2a3391cd |
| 07-Feb-2014 |
Stephen Boyd <sboyd@codeaurora.org> |
ARM: perf: add basic support for Krait CPU PMUs
Add basic support for the Krait CPU PMU. This allows us to use the architected functionality of the PMU.
This is based on code originally written by
ARM: perf: add basic support for Krait CPU PMUs
Add basic support for the Krait CPU PMU. This allows us to use the architected functionality of the PMU.
This is based on code originally written by Ashwin Chaugule and Neil Leeder [1].
[1] https://www.codeaurora.org/cgit/quic/la/kernel/msm/tree/arch/arm/kernel/perf_event_msm_krait.c?h=msm-3.4
Cc: Neil Leeder <nleeder@codeaurora.org> Cc: Ashwin Chaugule <ashwinc@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
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f2fe09b0 |
| 28-Feb-2013 |
Will Deacon <will.deacon@arm.com> |
ARM: 7663/1: perf: fix ARMv7 EVTYPE_MASK to include NSH bit
Masked out PMXEVTYPER.NSH means that we can't enable profiling at PL2, regardless of the settings in the HDCR.
This patch fixes the broke
ARM: 7663/1: perf: fix ARMv7 EVTYPE_MASK to include NSH bit
Masked out PMXEVTYPER.NSH means that we can't enable profiling at PL2, regardless of the settings in the HDCR.
This patch fixes the broken mask.
Cc: <stable@vger.kernel.org> Reported-by: Christoffer Dall <cdall@cs.columbia.edu> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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40c390c7 |
| 16-Jan-2013 |
Will Deacon <will.deacon@arm.com> |
ARM: perf: don't pretend to support counting of L1I writes
ARM has a harvard cache architecture and cannot write directly to the I-side.
This patch removes the L1I write events from the cache map (
ARM: perf: don't pretend to support counting of L1I writes
ARM has a harvard cache architecture and cannot write directly to the I-side.
This patch removes the L1I write events from the cache map (which previously returned *read* events in many cases).
Reported-by: Mike Williams <michael.williams@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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351a102d |
| 21-Dec-2012 |
Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
ARM: drivers: remove __dev* attributes.
CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed.
This change removes the use of __devinit, __devexit_p, __dev
ARM: drivers: remove __dev* attributes.
CONFIG_HOTPLUG is going away as an option. As a result, the __dev* markings need to be removed.
This change removes the use of __devinit, __devexit_p, __devinitdata, and __devexit from these drivers.
Based on patches originally written by Bill Pemberton, but redone by me in order to handle some of the coding style issues better, by hand.
Cc: Bill Pemberton <wfp5p@virginia.edu> Cc: Russell King <linux@arm.linux.org.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Revision tags: v3.7, v3.7-rc8, v3.7-rc7, v3.7-rc6, v3.7-rc5, v3.7-rc4, v3.7-rc3, v3.7-rc2, v3.7-rc1, v3.6, v3.6-rc7, v3.6-rc6, v3.6-rc5, v3.6-rc4, v3.6-rc3, v3.6-rc2, v3.6-rc1, v3.5 |
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#
7279adbd |
| 20-Jul-2012 |
Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com> |
ARM: perf: check ARMv7 counter validity on a per-pmu basis
Multi-cluster ARMv7 systems may have CPU PMUs with different number of counters.
This patch updates armv7_pmnc_counter_valid so that it ta
ARM: perf: check ARMv7 counter validity on a per-pmu basis
Multi-cluster ARMv7 systems may have CPU PMUs with different number of counters.
This patch updates armv7_pmnc_counter_valid so that it takes a pmu argument and checks the counter validity against that. We also remove a number of redundant counter checks whether the current PMU is not easily retrievable.
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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ed6f2a52 |
| 30-Jul-2012 |
Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com> |
ARM: perf: consistently use struct perf_event in arm_pmu functions
The arm_pmu functions have wildly varied parameters which can often be derived from struct perf_event.
This patch changes the arm_
ARM: perf: consistently use struct perf_event in arm_pmu functions
The arm_pmu functions have wildly varied parameters which can often be derived from struct perf_event.
This patch changes the arm_pmu function prototypes so that struct perf_event pointers are passed in preference to fields that can be derived from the event.
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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513c99ce |
| 31-Jul-2012 |
Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com> |
ARM: perf: allocate CPU PMU dynamically at probe time
Supporting multiple, heterogeneous CPU PMUs requires us to allocate the arm_pmu structures dynamically as the devices are probed.
This patch re
ARM: perf: allocate CPU PMU dynamically at probe time
Supporting multiple, heterogeneous CPU PMUs requires us to allocate the arm_pmu structures dynamically as the devices are probed.
This patch removes the static structure definitions for each CPU PMU type and instead passes pointers to the PMU-specific init functions.
Signed-off-by: Sudeep KarkadaNagesha <Sudeep.KarkadaNagesha@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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#
6dbc0029 |
| 29-Jul-2012 |
Will Deacon <will.deacon@arm.com> |
ARM: perf: prepare for moving CPU PMU code into separate file
The CPU PMU code is tightly coupled with generic ARM PMU handling code. This makes it cumbersome when trying to add support for other AR
ARM: perf: prepare for moving CPU PMU code into separate file
The CPU PMU code is tightly coupled with generic ARM PMU handling code. This makes it cumbersome when trying to add support for other ARM PMUs (e.g. interconnect, L2 cache controller, bus) as the generic parts of the code are not readily reusable.
This patch cleans up perf_event.c so that reusable code is exposed via header files to other potential PMU drivers. The CPU code is consistently named to identify it as such and also to prepare for moving it into a separate file.
Signed-off-by: Will Deacon <will.deacon@arm.com>
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04236f9f |
| 28-Jul-2012 |
Will Deacon <will.deacon@arm.com> |
ARM: perf: probe devicetree in preference to current CPU
The CPU PMU is probed using the current cpuid information as part of the early_initcall initialising the architecture perf backend. For archi
ARM: perf: probe devicetree in preference to current CPU
The CPU PMU is probed using the current cpuid information as part of the early_initcall initialising the architecture perf backend. For architectures without NMI (such as ARM), this does not need to be performed early and can be deferred to the driver probe callback. This also allows us to probe the devicetree in preference to parsing the current cpuid, which may be invalid on a big.LITTLE multi-cluster system.
This patch defers the PMU probing and uses the devicetree information when available.
Signed-off-by: Will Deacon <will.deacon@arm.com>
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Revision tags: v3.5-rc7, v3.5-rc6 |
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4295b898 |
| 06-Jul-2012 |
Will Deacon <will.deacon@arm.com> |
ARM: 7448/1: perf: remove arm_perf_pmu_ids global enumeration
In order to provide PMU name strings compatible with the OProfile user ABI, an enumeration of all PMUs is currently used by perf to iden
ARM: 7448/1: perf: remove arm_perf_pmu_ids global enumeration
In order to provide PMU name strings compatible with the OProfile user ABI, an enumeration of all PMUs is currently used by perf to identify each PMU uniquely. Unfortunately, this does not scale well in the presence of multiple PMUs and creates a single, global namespace across all PMUs in the system.
This patch removes the enumeration and instead uses the name string for the PMU to map onto the OProfile variant. perf_pmu_name is implemented for CPU PMUs, which is all that OProfile cares about anyway.
Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Revision tags: v3.5-rc5, v3.5-rc4, v3.5-rc3, v3.5-rc2, v3.5-rc1, v3.4, v3.4-rc7, v3.4-rc6, v3.4-rc5, v3.4-rc4, v3.4-rc3, v3.4-rc2 |
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fd0d000b |
| 02-Apr-2012 |
Robert Richter <robert.richter@amd.com> |
perf: Pass last sampling period to perf_sample_data_init()
We always need to pass the last sample period to perf_sample_data_init(), otherwise the event distribution will be wrong. Thus, modifiyng t
perf: Pass last sampling period to perf_sample_data_init()
We always need to pass the last sample period to perf_sample_data_init(), otherwise the event distribution will be wrong. Thus, modifiyng the function interface with the required period as argument. So basically a pattern like this:
perf_sample_data_init(&data, ~0ULL); data.period = event->hw.last_period;
will now be like that:
perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
Avoids unininitialized data.period and simplifies code.
Signed-off-by: Robert Richter <robert.richter@amd.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1333390758-10893-3-git-send-email-robert.richter@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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Revision tags: v3.4-rc1, v3.3, v3.3-rc7, v3.3-rc6, v3.3-rc5, v3.3-rc4, v3.3-rc3 |
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d33c88c6 |
| 03-Feb-2012 |
Will Deacon <will.deacon@arm.com> |
ARM: 7315/1: perf: add support for the Cortex-A7 PMU
Cortex-A7 implements an ARMv7-compatible PMU compliant with the PMUv2 architecture specification.
This patch adds support for the PMU to the ARM
ARM: 7315/1: perf: add support for the Cortex-A7 PMU
Cortex-A7 implements an ARMv7-compatible PMU compliant with the PMUv2 architecture specification.
This patch adds support for the PMU to the ARM perf backend.
Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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f6f5a30c |
| 06-Mar-2012 |
Will Deacon <will.deacon@arm.com> |
ARM: 7356/1: perf: check that we have an event in the PMU IRQ handlers
The PMU IRQ handlers in perf assume that if a counter has overflowed then perf must be responsible. In the paranoid world of cr
ARM: 7356/1: perf: check that we have an event in the PMU IRQ handlers
The PMU IRQ handlers in perf assume that if a counter has overflowed then perf must be responsible. In the paranoid world of crazy hardware, this could be false, so check that we do have a valid event before attempting to dereference NULL in the interrupt path.
Cc: <stable@vger.kernel.org> Signed-off-by: Ming Lei <tom.leiming@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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99c1745b |
| 06-Mar-2012 |
Will Deacon <will.deacon@arm.com> |
ARM: 7355/1: perf: clear overflow flag when disabling counter on ARMv7 PMU
When disabling a counter on an ARMv7 PMU, we should also clear the overflow flag in case an overflow occurred whilst stoppi
ARM: 7355/1: perf: clear overflow flag when disabling counter on ARMv7 PMU
When disabling a counter on an ARMv7 PMU, we should also clear the overflow flag in case an overflow occurred whilst stopping the counter. This prevents a spurious overflow being picked up later and leading to either false accounting or a NULL dereference.
Cc: <stable@vger.kernel.org> Reported-by: Ming Lei <tom.leiming@gmail.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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57273471 |
| 06-Mar-2012 |
Will Deacon <will.deacon@arm.com> |
ARM: 7354/1: perf: limit sample_period to half max_period in non-sampling mode
On ARM, the PMU does not stop counting after an overflow and therefore IRQ latency affects the new counter value read b
ARM: 7354/1: perf: limit sample_period to half max_period in non-sampling mode
On ARM, the PMU does not stop counting after an overflow and therefore IRQ latency affects the new counter value read by the kernel. This is significant for non-sampling runs where it is possible for the new value to overtake the previous one, causing the delta to be out by up to max_period events.
Commit a737823d ("ARM: 6835/1: perf: ensure overflows aren't missed due to IRQ latency") attempted to fix this problem by allowing interrupt handlers to pass an overflow flag to the event update function, causing the overflow calculation to assume that the counter passed through zero when going from prev to new. Unfortunately, this doesn't work when overflow occurs on the perf_task_tick path because we have the flag cleared and end up computing a large negative delta.
This patch removes the overflow flag from armpmu_event_update and instead limits the sample_period to half of the max_period for non-sampling profiling runs.
Cc: <stable@vger.kernel.org> Signed-off-by: Ming Lei <ming.lei@canonical.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Revision tags: v3.3-rc2 |
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91756acb |
| 25-Jan-2012 |
Will Deacon <will.deacon@arm.com> |
ARM: 7303/1: perf: add empty NODE event definitions for Cortex-A5 and Cortex-A15
Commit 89d6c0b5 ("perf, arch: Add generic NODE cache events") added empty NODE event definitions for the ARM PMU impl
ARM: 7303/1: perf: add empty NODE event definitions for Cortex-A5 and Cortex-A15
Commit 89d6c0b5 ("perf, arch: Add generic NODE cache events") added empty NODE event definitions for the ARM PMU implementations. This was merged along with Cortex-A5 and Cortex-A15 PMU support, so they missed out on the original patch.
This patch adds the empty definitions to Cortex-A5 and Cortex-A15.
Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Revision tags: v3.3-rc1, v3.2, v3.2-rc7, v3.2-rc6, v3.2-rc5, v3.2-rc4, v3.2-rc3, v3.2-rc2, v3.2-rc1, v3.1, v3.1-rc10, v3.1-rc9 |
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0445e7a5 |
| 29-Sep-2011 |
Will Deacon <will.deacon@arm.com> |
ARM: perf: add support for stalled cycle ABI events
Commit 8f622422 ("perf events: Add generic front-end and back-end stalled cycle event definitions") added two new ABI events for counting stalled
ARM: perf: add support for stalled cycle ABI events
Commit 8f622422 ("perf events: Add generic front-end and back-end stalled cycle event definitions") added two new ABI events for counting stalled cycles.
This patch adds support for these new events to the ARM perf implementation.
Cc: Jamie Iles <jamie@jamieiles.com> Cc: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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#
4d301512 |
| 29-Sep-2011 |
Will Deacon <will.deacon@arm.com> |
ARM: perf: clean and update ARMv7 event numbers
This patch updates the ARMv7 perf event numbers so that:
(1) A consistent naming scheme is used between different CPUs.
(2) Only events actually use
ARM: perf: clean and update ARMv7 event numbers
This patch updates the ARMv7 perf event numbers so that:
(1) A consistent naming scheme is used between different CPUs.
(2) Only events actually used by Linux are described.
(3) Where possible, architected events are used in preference to CPU-specific events.
This results in the removal of a load of unused, hardcoded data and makes it more clear as to which events are supported on each PMU.
Cc: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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29a541f6 |
| 03-Oct-2011 |
Will Deacon <will.deacon@arm.com> |
ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9
Using COHERENT_LINE_{MISS,HIT} for cache misses and references respectively is completely wrong. Instead, use the L1D events which are a better
ARM: 7117/1: perf: fix HW_CACHE_* events on Cortex-A9
Using COHERENT_LINE_{MISS,HIT} for cache misses and references respectively is completely wrong. Instead, use the L1D events which are a better and more useful approximation despite ignoring instruction traffic.
Reported-by: Alasdair Grant <alasdair.grant@arm.com> Reported-by: Matt Horsnell <matt.horsnell@arm.com> Reported-by: Michael Williams <michael.williams@arm.com> Cc: stable@kernel.org Cc: Jean Pihet <j-pihet@ti.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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