ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.

The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EE

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EEPROM, so let's add support for using it.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.

The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EE

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EEPROM, so let's add support for using it.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.

The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EE

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EEPROM, so let's add support for using it.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.

The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EE

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EEPROM, so let's add support for using it.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.

The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EE

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EEPROM, so let's add support for using it.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.

The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EE

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EEPROM, so let's add support for using it.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.

The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EE

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EEPROM, so let's add support for using it.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.

The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EE

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EEPROM, so let's add support for using it.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.

The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EE

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EEPROM, so let's add support for using it.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.

The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EE

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EEPROM, so let's add support for using it.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
externa

ARM: dts: aspeed: asrock: Add BIOS SPI flash chips

On e3c246d4i, e3c256d4i, romed8hm3, and spc621d8hm3 the host firmware
flash is accessible to the BMC via the AST2500 SPI1 interface with an
external GPIO-controlled mux switching the flash chip between the host
and the BMC.

The default state of the mux GPIO leaves it connected to the host, so
the BMC's attempt to bind a driver to it during its boot sequence will
fail, but a write to a sysfs 'bind' file after toggling the mux GPIO
(along with whatever other preparatory steps are required) can later
allow it to be attached and accessed by the BMC. It's not an ideal
arrangement, but in the absence of DT overlays or any other
alternative it is at least a functional one, if somewhat clumsily so.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EE

ARM: dts: aspeed: asrock: Use MAC address from FRU EEPROM

Like the more recently added ASRock BMC platforms, e3c246d4i and
romed8hm3 also have the BMC's MAC address available in the baseboard
FRU EEPROM, so let's add support for using it.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>

show more ...

ARM: dts: Move .dts files to vendor sub-directories

The arm dts directory has grown to 1559 boards which makes it a bit
unwieldy to maintain and use. Past attempts stalled out due to plans to
move .

ARM: dts: Move .dts files to vendor sub-directories

The arm dts directory has grown to 1559 boards which makes it a bit
unwieldy to maintain and use. Past attempts stalled out due to plans to
move .dts files out of the kernel tree. Doing that is no longer planned
(any time soon at least), so let's go ahead and group .dts files by
vendors. This move aligns arm with arm64 .dts file structure.

There's no change to dtbs_install as the flat structure is maintained on
install.

The naming of vendor directories is roughly in this order of preference:
- Matching original and current SoC vendor prefix/name (e.g. ti, qcom)
- Current vendor prefix/name if still actively sold (SoCs which have
been aquired) (e.g. nxp/imx)
- Existing platform name for older platforms not sold/maintained by any
company (e.g. gemini, nspire)

The whole move was scripted with the exception of MAINTAINERS and a few
makefile fixups.

Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Michal Simek <michal.simek@amd.com> #Xilinx
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Paul Barker <paul.barker@sancloud.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Wei Xu <xuwei5@hisilicon.com> #hisilicon
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Nick Hawkins <nick.hawkins@hpe.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Peter Rosin <peda@axentia.se>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com> #broadcom
Acked-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Patrice Chotard <patrice.chotard@foss.st.com>
Acked-by: Romain Perier <romain.perier@gmail.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Acked-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Enric Balletbo i Serra <eballetbo@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>

show more ...