1# X86 power control 2 3This repository contains an OpenBMC compliant implementation of power control 4for x86 servers. It relies on a number of features to do its job. It has several 5intentional design goals. 6 71. The BMC should maintain the Host state machine internally, and be able to 8 track state changes. 92. The implementation should either give the requested power control result, or 10 should log an error on the failure it detected. 113. The BMC should support all the common operations, hard power on/off/cycle, 12 soft power on/off/cycle. 13 14This daemon has been successfully used on a variety of server platforms; it 15should be able to support platforms with power control GPIOs similar to those in 16its config file. 17 18x86-power-control uses default json file (power-config-host0.json) for GPIO 19configuration. However this can be customized by producing your own 20power-config-host0.json file. 21 22## Signal Definitions 23 24Definitions can be configured by two type: GPIO and DBUS 25 26### GPIO 27 28For the platform having direct GPIO access can use the type GPIO and define like 29below. 30 31```json 32{ 33 "Name": "PostComplete", 34 "LineName": "POST_COMPLETE", 35 "Type": "GPIO" 36} 37``` 38 39### DBUS 40 41For the platform not having direct GPIO access can use dbus based event monitor 42by using the type DBUS. 43 44```json 45{ 46 "Name": "PowerButton", 47 "DbusName": "xyz.openbmc_project.Chassis.Event", 48 "Path": "/xyz/openbmc_project/Chassis/Event", 49 "Interface": "xyz.openbmc_project.Chassis.Event", 50 "Property": "PowerButton_Host1", 51 "Type": "DBUS" 52} 53``` 54 55x86-power-control will monitor the property change from the given DbusName and 56take appropriate action. \*define Property as a bool variable. 57 58Caveats: This implementation does not currently implement the common targets 59that other implementations do. There were several attempts to, but all ended in 60timing issues and boot inconsistencies during stress operations. 61 62## Build Options 63 64### chassis-system-reset 65 66Enable chassis system power reset to allow removing power and restoring back. 67 68### use-plt-rst 69 70The POST Complete GPIO is usually held asserted by BIOS after POST complete and 71de-asserts on reset. This de-assert behavior is currently used to detect warm 72resets. 73 74Some systems are adding support for a PLT_RST eSPI signal that can be used to 75more accurately detect warm resets. When this option is enabled, 76x86-power-control will use PLT_RST to detect warm resets instead of POST 77Complete. 78 79See <https://github.com/Intel-BMC/host-misc-comm-manager> for implementation 80example. 81