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README.md

1 # X86 power control
2 
3 This repository contains an OpenBMC compliant implementation of power control
4 for x86 servers. It relies on a number of features to do its job. It has several
5 intentional design goals.
6 
7 1. The BMC should maintain the Host state machine internally, and be able to
8    track state changes.
9 2. The implementation should either give the requested power control result, or
10    should log an error on the failure it detected.
11 3. The BMC should support all the common operations, hard power on/off/cycle,
12    soft power on/off/cycle.
13 
14 This daemon has been successfully used on a variety of server platforms; it
15 should be able to support platforms with power control GPIOs similar to those in
16 its config file.
17 
18 x86-power-control uses default json file (power-config-host0.json) for GPIO
19 configuration. However this can be customized by producing your own
20 power-config-host0.json file.
21 
22 ## Signal Definitions
23 
24 Definitions can be configured by two type: GPIO and DBUS
25 
26 ### GPIO
27 
28 For the platform having direct GPIO access can use the type GPIO and define like
29 below.
30 
31 ```json
32 {
33   "Name": "PostComplete",
34   "LineName": "POST_COMPLETE",
35   "Type": "GPIO"
36 }
37 ```
38 
39 ### DBUS
40 
41 For the platform not having direct GPIO access can use dbus based event monitor
42 by using the type DBUS.
43 
44 ```json
45 {
46   "Name": "PowerButton",
47   "DbusName": "xyz.openbmc_project.Chassis.Event",
48   "Path": "/xyz/openbmc_project/Chassis/Event",
49   "Interface": "xyz.openbmc_project.Chassis.Event",
50   "Property": "PowerButton_Host1",
51   "Type": "DBUS"
52 }
53 ```
54 
55 x86-power-control will monitor the property change from the given DbusName and
56 take appropriate action. \*define Property as a bool variable.
57 
58 Caveats: This implementation does not currently implement the common targets
59 that other implementations do. There were several attempts to, but all ended in
60 timing issues and boot inconsistencies during stress operations.
61 
62 ## Build Options
63 
64 ### chassis-system-reset
65 
66 Enable chassis system power reset to allow removing power and restoring back.
67 
68 ### use-plt-rst
69 
70 The POST Complete GPIO is usually held asserted by BIOS after POST complete and
71 de-asserts on reset. This de-assert behavior is currently used to detect warm
72 resets.
73 
74 Some systems are adding support for a PLT_RST eSPI signal that can be used to
75 more accurately detect warm resets. When this option is enabled,
76 x86-power-control will use PLT_RST to detect warm resets instead of POST
77 Complete.
78 
79 See <https://github.com/Intel-BMC/host-misc-comm-manager> for implementation
80 example.
81