1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2016 Michal Simek <michals@xilinx.com> 4 * Copyright (C) 2015 Nathan Rossi <nathan@nathanrossi.com> 5 * 6 * The following Boot Header format/structures and values are defined in the 7 * following documents: 8 * * ug1085 ZynqMP TRM doc v1.4 (Chapter 11, Table 11-4) 9 * * ug1137 ZynqMP Software Developer Guide v6.0 (Chapter 16) 10 */ 11 12 #ifndef _ZYNQMPIMAGE_H_ 13 #define _ZYNQMPIMAGE_H_ 14 15 #include <stdint.h> 16 17 #define HEADER_INTERRUPT_DEFAULT (cpu_to_le32(0xeafffffe)) 18 #define HEADER_REGINIT_NULL (cpu_to_le32(0xffffffff)) 19 #define HEADER_WIDTHDETECTION (cpu_to_le32(0xaa995566)) 20 #define HEADER_IMAGEIDENTIFIER (cpu_to_le32(0x584c4e58)) 21 #define HEADER_CPU_SELECT_MASK (0x3 << 10) 22 #define HEADER_CPU_SELECT_R5_SINGLE (0x0 << 10) 23 #define HEADER_CPU_SELECT_A53_32BIT (0x1 << 10) 24 #define HEADER_CPU_SELECT_A53_64BIT (0x2 << 10) 25 #define HEADER_CPU_SELECT_R5_DUAL (0x3 << 10) 26 27 enum { 28 ENCRYPTION_EFUSE = 0xa5c3c5a3, 29 ENCRYPTION_OEFUSE = 0xa5c3c5a7, 30 ENCRYPTION_BBRAM = 0x3a5c3c5a, 31 ENCRYPTION_OBBRAM = 0xa35c7ca5, 32 ENCRYPTION_NONE = 0x0, 33 }; 34 35 struct zynqmp_reginit { 36 uint32_t address; 37 uint32_t data; 38 }; 39 40 #define HEADER_INTERRUPT_VECTORS 8 41 #define HEADER_REGINITS 256 42 43 struct image_header_table { 44 uint32_t version; /* 0x00 */ 45 uint32_t nr_parts; /* 0x04 */ 46 uint32_t partition_header_offset; /* 0x08, divided by 4 */ 47 uint32_t image_header_offset; /* 0x0c, divided by 4 */ 48 uint32_t auth_certificate_offset; /* 0x10 */ 49 uint32_t boot_device; /* 0x14 */ 50 uint32_t __reserved1[9]; /* 0x18 - 0x38 */ 51 uint32_t checksum; /* 0x3c */ 52 }; 53 54 #define PART_ATTR_VEC_LOCATION 0x800000 55 #define PART_ATTR_BS_BLOCK_SIZE_MASK 0x700000 56 #define PART_ATTR_BS_BLOCK_SIZE_DEFAULT 0x000000 57 #define PART_ATTR_BS_BLOCK_SIZE_8MB 0x400000 58 #define PART_ATTR_BIG_ENDIAN 0x040000 59 #define PART_ATTR_PART_OWNER_MASK 0x030000 60 #define PART_ATTR_PART_OWNER_FSBL 0x000000 61 #define PART_ATTR_PART_OWNER_UBOOT 0x010000 62 #define PART_ATTR_RSA_SIG 0x008000 63 #define PART_ATTR_CHECKSUM_MASK 0x007000 64 #define PART_ATTR_CHECKSUM_NONE 0x000000 65 #define PART_ATTR_CHECKSUM_MD5 0x001000 66 #define PART_ATTR_CHECKSUM_SHA2 0x002000 67 #define PART_ATTR_CHECKSUM_SHA3 0x003000 68 #define PART_ATTR_DEST_CPU_SHIFT 8 69 #define PART_ATTR_DEST_CPU_MASK 0x000f00 70 #define PART_ATTR_DEST_CPU_NONE 0x000000 71 #define PART_ATTR_DEST_CPU_A53_0 0x000100 72 #define PART_ATTR_DEST_CPU_A53_1 0x000200 73 #define PART_ATTR_DEST_CPU_A53_2 0x000300 74 #define PART_ATTR_DEST_CPU_A53_3 0x000400 75 #define PART_ATTR_DEST_CPU_R5_0 0x000500 76 #define PART_ATTR_DEST_CPU_R5_1 0x000600 77 #define PART_ATTR_DEST_CPU_R5_L 0x000700 78 #define PART_ATTR_DEST_CPU_PMU 0x000800 79 #define PART_ATTR_ENCRYPTED 0x000080 80 #define PART_ATTR_DEST_DEVICE_SHIFT 4 81 #define PART_ATTR_DEST_DEVICE_MASK 0x000070 82 #define PART_ATTR_DEST_DEVICE_NONE 0x000000 83 #define PART_ATTR_DEST_DEVICE_PS 0x000010 84 #define PART_ATTR_DEST_DEVICE_PL 0x000020 85 #define PART_ATTR_DEST_DEVICE_PMU 0x000030 86 #define PART_ATTR_DEST_DEVICE_XIP 0x000040 87 #define PART_ATTR_A53_EXEC_AARCH32 0x000008 88 #define PART_ATTR_TARGET_EL_SHIFT 1 89 #define PART_ATTR_TARGET_EL_MASK 0x000006 90 #define PART_ATTR_TZ_SECURE 0x000001 91 92 static const char *dest_cpus[0x10] = { 93 "none", "a5x-0", "a5x-1", "a5x-2", "a5x-3", "r5-0", "r5-1", 94 "r5-lockstep", "pmu", "unknown", "unknown", "unknown", "unknown", 95 "unknown", "unknown", "unknown" 96 }; 97 98 struct partition_header { 99 uint32_t len_enc; /* 0x00, divided by 4 */ 100 uint32_t len_unenc; /* 0x04, divided by 4 */ 101 uint32_t len; /* 0x08, divided by 4 */ 102 uint32_t next_partition_offset; /* 0x0c */ 103 uint64_t entry_point; /* 0x10 */ 104 uint64_t load_address; /* 0x18 */ 105 uint32_t offset; /* 0x20, divided by 4 */ 106 uint32_t attributes; /* 0x24 */ 107 uint32_t __reserved1; /* 0x28 */ 108 uint32_t checksum_offset; /* 0x2c, divided by 4 */ 109 uint32_t __reserved2; /* 0x30 */ 110 uint32_t auth_certificate_offset; /* 0x34 */ 111 uint32_t __reserved3; /* 0x38 */ 112 uint32_t checksum; /* 0x3c */ 113 }; 114 115 struct zynqmp_header { 116 uint32_t interrupt_vectors[HEADER_INTERRUPT_VECTORS]; /* 0x0 */ 117 uint32_t width_detection; /* 0x20 */ 118 uint32_t image_identifier; /* 0x24 */ 119 uint32_t encryption; /* 0x28 */ 120 uint32_t image_load; /* 0x2c */ 121 uint32_t image_offset; /* 0x30 */ 122 uint32_t pfw_image_length; /* 0x34 */ 123 uint32_t total_pfw_image_length; /* 0x38 */ 124 uint32_t image_size; /* 0x3c */ 125 uint32_t image_stored_size; /* 0x40 */ 126 uint32_t image_attributes; /* 0x44 */ 127 uint32_t checksum; /* 0x48 */ 128 uint32_t __reserved1[19]; /* 0x4c */ 129 uint32_t image_header_table_offset; /* 0x98 */ 130 uint32_t __reserved2[7]; /* 0x9c */ 131 struct zynqmp_reginit register_init[HEADER_REGINITS]; /* 0xb8 */ 132 uint32_t __reserved4[66]; /* 0x9c0 */ 133 }; 134 135 void zynqmpimage_default_header(struct zynqmp_header *ptr); 136 void zynqmpimage_print_header(const void *ptr); 137 138 #endif /* _ZYNQMPIMAGE_H_ */ 139