1 /* 2 * (C) Copyright 2008 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef _KWBIMAGE_H_ 10 #define _KWBIMAGE_H_ 11 12 #include <stdint.h> 13 14 #define KWBIMAGE_MAX_CONFIG ((0x1dc - 0x20)/sizeof(struct reg_config)) 15 #define MAX_TEMPBUF_LEN 32 16 17 /* NAND ECC Mode */ 18 #define IBR_HDR_ECC_DEFAULT 0x00 19 #define IBR_HDR_ECC_FORCED_HAMMING 0x01 20 #define IBR_HDR_ECC_FORCED_RS 0x02 21 #define IBR_HDR_ECC_DISABLED 0x03 22 23 /* Boot Type - block ID */ 24 #define IBR_HDR_I2C_ID 0x4D 25 #define IBR_HDR_SPI_ID 0x5A 26 #define IBR_HDR_NAND_ID 0x8B 27 #define IBR_HDR_SATA_ID 0x78 28 #define IBR_HDR_PEX_ID 0x9C 29 #define IBR_HDR_UART_ID 0x69 30 #define IBR_DEF_ATTRIB 0x00 31 32 enum kwbimage_cmd { 33 CMD_INVALID, 34 CMD_BOOT_FROM, 35 CMD_NAND_ECC_MODE, 36 CMD_NAND_PAGE_SIZE, 37 CMD_SATA_PIO_MODE, 38 CMD_DDR_INIT_DELAY, 39 CMD_DATA 40 }; 41 42 enum kwbimage_cmd_types { 43 CFG_INVALID = -1, 44 CFG_COMMAND, 45 CFG_DATA0, 46 CFG_DATA1 47 }; 48 49 /* typedefs */ 50 typedef struct bhr_t { 51 uint8_t blockid; /*0 */ 52 uint8_t nandeccmode; /*1 */ 53 uint16_t nandpagesize; /*2-3 */ 54 uint32_t blocksize; /*4-7 */ 55 uint32_t rsvd1; /*8-11 */ 56 uint32_t srcaddr; /*12-15 */ 57 uint32_t destaddr; /*16-19 */ 58 uint32_t execaddr; /*20-23 */ 59 uint8_t satapiomode; /*24 */ 60 uint8_t rsvd3; /*25 */ 61 uint16_t ddrinitdelay; /*26-27 */ 62 uint16_t rsvd2; /*28-29 */ 63 uint8_t ext; /*30 */ 64 uint8_t checkSum; /*31 */ 65 } bhr_t, *pbhr_t; 66 67 struct reg_config { 68 uint32_t raddr; 69 uint32_t rdata; 70 }; 71 72 typedef struct extbhr_t { 73 uint32_t dramregsoffs; 74 uint8_t rsrvd1[0x20 - sizeof(uint32_t)]; 75 struct reg_config rcfg[KWBIMAGE_MAX_CONFIG]; 76 uint8_t rsrvd2[7]; 77 uint8_t checkSum; 78 } extbhr_t, *pextbhr_t; 79 80 struct kwb_header { 81 bhr_t kwb_hdr; 82 extbhr_t kwb_exthdr; 83 }; 84 85 /* 86 * functions 87 */ 88 void init_kwb_image_type (void); 89 90 #endif /* _KWBIMAGE_H_ */ 91