xref: /openbmc/u-boot/tools/kwbimage.h (revision 971a54193c9a90a6651064c4a7879e3568e9e7b8)
1  /*
2   * (C) Copyright 2008
3   * Marvell Semiconductor <www.marvell.com>
4   * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
5   *
6   * SPDX-License-Identifier:	GPL-2.0+
7   */
8  
9  #ifndef _KWBIMAGE_H_
10  #define _KWBIMAGE_H_
11  
12  #include <compiler.h>
13  #include <stdint.h>
14  
15  #define KWBIMAGE_MAX_CONFIG	((0x1dc - 0x20)/sizeof(struct reg_config))
16  #define MAX_TEMPBUF_LEN		32
17  
18  /* NAND ECC Mode */
19  #define IBR_HDR_ECC_DEFAULT		0x00
20  #define IBR_HDR_ECC_FORCED_HAMMING	0x01
21  #define IBR_HDR_ECC_FORCED_RS  		0x02
22  #define IBR_HDR_ECC_DISABLED  		0x03
23  
24  /* Boot Type - block ID */
25  #define IBR_HDR_I2C_ID			0x4D
26  #define IBR_HDR_SPI_ID			0x5A
27  #define IBR_HDR_NAND_ID			0x8B
28  #define IBR_HDR_SATA_ID			0x78
29  #define IBR_HDR_PEX_ID			0x9C
30  #define IBR_HDR_UART_ID			0x69
31  #define IBR_DEF_ATTRIB	 		0x00
32  
33  #define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
34  
35  /* Structure of the main header, version 0 (Kirkwood, Dove) */
36  struct main_hdr_v0 {
37  	uint8_t  blockid;		/* 0x0       */
38  	uint8_t  nandeccmode;		/* 0x1       */
39  	uint16_t nandpagesize;		/* 0x2-0x3   */
40  	uint32_t blocksize;		/* 0x4-0x7   */
41  	uint32_t rsvd1;			/* 0x8-0xB   */
42  	uint32_t srcaddr;		/* 0xC-0xF   */
43  	uint32_t destaddr;		/* 0x10-0x13 */
44  	uint32_t execaddr;		/* 0x14-0x17 */
45  	uint8_t  satapiomode;		/* 0x18      */
46  	uint8_t  rsvd3;			/* 0x19      */
47  	uint16_t ddrinitdelay;		/* 0x1A-0x1B */
48  	uint16_t rsvd2;			/* 0x1C-0x1D */
49  	uint8_t  ext;			/* 0x1E      */
50  	uint8_t  checksum;		/* 0x1F      */
51  };
52  
53  struct ext_hdr_v0_reg {
54  	uint32_t raddr;
55  	uint32_t rdata;
56  };
57  
58  #define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
59  
60  struct ext_hdr_v0 {
61  	uint32_t              offset;
62  	uint8_t               reserved[0x20 - sizeof(uint32_t)];
63  	struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
64  	uint8_t               reserved2[7];
65  	uint8_t               checksum;
66  };
67  
68  struct kwb_header {
69  	struct main_hdr_v0	kwb_hdr;
70  	struct ext_hdr_v0	kwb_exthdr;
71  };
72  
73  /* Structure of the main header, version 1 (Armada 370/38x/XP) */
74  struct main_hdr_v1 {
75  	uint8_t  blockid;               /* 0x0       */
76  	uint8_t  flags;                 /* 0x1       */
77  	uint16_t reserved2;             /* 0x2-0x3   */
78  	uint32_t blocksize;             /* 0x4-0x7   */
79  	uint8_t  version;               /* 0x8       */
80  	uint8_t  headersz_msb;          /* 0x9       */
81  	uint16_t headersz_lsb;          /* 0xA-0xB   */
82  	uint32_t srcaddr;               /* 0xC-0xF   */
83  	uint32_t destaddr;              /* 0x10-0x13 */
84  	uint32_t execaddr;              /* 0x14-0x17 */
85  	uint8_t  options;               /* 0x18      */
86  	uint8_t  nandblocksize;         /* 0x19      */
87  	uint8_t  nandbadblklocation;    /* 0x1A      */
88  	uint8_t  reserved4;             /* 0x1B      */
89  	uint16_t reserved5;             /* 0x1C-0x1D */
90  	uint8_t  ext;                   /* 0x1E      */
91  	uint8_t  checksum;              /* 0x1F      */
92  };
93  
94  /*
95   * Main header options
96   */
97  #define MAIN_HDR_V1_OPT_BAUD_DEFAULT	0
98  #define MAIN_HDR_V1_OPT_BAUD_2400	0x1
99  #define MAIN_HDR_V1_OPT_BAUD_4800	0x2
100  #define MAIN_HDR_V1_OPT_BAUD_9600	0x3
101  #define MAIN_HDR_V1_OPT_BAUD_19200	0x4
102  #define MAIN_HDR_V1_OPT_BAUD_38400	0x5
103  #define MAIN_HDR_V1_OPT_BAUD_57600	0x6
104  #define MAIN_HDR_V1_OPT_BAUD_115200	0x7
105  
106  /*
107   * Header for the optional headers, version 1 (Armada 370, Armada XP)
108   */
109  struct opt_hdr_v1 {
110  	uint8_t  headertype;
111  	uint8_t  headersz_msb;
112  	uint16_t headersz_lsb;
113  	char     data[0];
114  };
115  
116  /*
117   * Public Key data in DER format
118   */
119  struct pubkey_der_v1 {
120  	uint8_t key[524];
121  };
122  
123  /*
124   * Signature (RSA 2048)
125   */
126  struct sig_v1 {
127  	uint8_t sig[256];
128  };
129  
130  /*
131   * Structure of secure header (Armada 38x)
132   */
133  struct secure_hdr_v1 {
134  	uint8_t  headertype;		/* 0x0 */
135  	uint8_t  headersz_msb;		/* 0x1 */
136  	uint16_t headersz_lsb;		/* 0x2 - 0x3 */
137  	uint32_t reserved1;		/* 0x4 - 0x7 */
138  	struct pubkey_der_v1 kak;	/* 0x8 - 0x213 */
139  	uint8_t  jtag_delay;		/* 0x214 */
140  	uint8_t  reserved2;		/* 0x215 */
141  	uint16_t reserved3;		/* 0x216 - 0x217 */
142  	uint32_t boxid;			/* 0x218 - 0x21B */
143  	uint32_t flashid;		/* 0x21C - 0x21F */
144  	struct sig_v1 hdrsig;		/* 0x220 - 0x31F */
145  	struct sig_v1 imgsig;		/* 0x320 - 0x41F */
146  	struct pubkey_der_v1 csk[16];	/* 0x420 - 0x24DF */
147  	struct sig_v1 csksig;		/* 0x24E0 - 0x25DF */
148  	uint8_t  next;			/* 0x25E0 */
149  	uint8_t  reserved4;		/* 0x25E1 */
150  	uint16_t reserved5;		/* 0x25E2 - 0x25E3 */
151  };
152  
153  /*
154   * Various values for the opt_hdr_v1->headertype field, describing the
155   * different types of optional headers. The "secure" header contains
156   * informations related to secure boot (encryption keys, etc.). The
157   * "binary" header contains ARM binary code to be executed prior to
158   * executing the main payload (usually the bootloader). This is
159   * typically used to execute DDR3 training code. The "register" header
160   * allows to describe a set of (address, value) tuples that are
161   * generally used to configure the DRAM controller.
162   */
163  #define OPT_HDR_V1_SECURE_TYPE   0x1
164  #define OPT_HDR_V1_BINARY_TYPE   0x2
165  #define OPT_HDR_V1_REGISTER_TYPE 0x3
166  
167  #define KWBHEADER_V1_SIZE(hdr) \
168  	(((hdr)->headersz_msb << 16) | le16_to_cpu((hdr)->headersz_lsb))
169  
170  enum kwbimage_cmd {
171  	CMD_INVALID,
172  	CMD_BOOT_FROM,
173  	CMD_NAND_ECC_MODE,
174  	CMD_NAND_PAGE_SIZE,
175  	CMD_SATA_PIO_MODE,
176  	CMD_DDR_INIT_DELAY,
177  	CMD_DATA
178  };
179  
180  enum kwbimage_cmd_types {
181  	CFG_INVALID = -1,
182  	CFG_COMMAND,
183  	CFG_DATA0,
184  	CFG_DATA1
185  };
186  
187  /*
188   * functions
189   */
190  void init_kwb_image_type (void);
191  
192  /*
193   * Byte 8 of the image header contains the version number. In the v0
194   * header, byte 8 was reserved, and always set to 0. In the v1 header,
195   * byte 8 has been changed to a proper field, set to 1.
196   */
197  static inline unsigned int image_version(void *header)
198  {
199  	unsigned char *ptr = header;
200  	return ptr[8];
201  }
202  
203  #endif /* _KWBIMAGE_H_ */
204