xref: /openbmc/u-boot/post/lib_powerpc/threex.c (revision 843a7ee8)
1 /*
2  * (C) Copyright 2002
3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  */
23 
24 #include <common.h>
25 
26 /*
27  * CPU test
28  * Ternary instructions		instr rA,rS,rB
29  *
30  * Logic instructions:		or, orc, xor, nand, nor, eqv
31  * Shift instructions:		slw, srw, sraw
32  *
33  * The test contains a pre-built table of instructions, operands and
34  * expected results. For each table entry, the test will cyclically use
35  * different sets of operand registers and result registers.
36  */
37 
38 #include <post.h>
39 #include "cpu_asm.h"
40 
41 #if CONFIG_POST & CONFIG_SYS_POST_CPU
42 
43 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
44     ulong op2);
45 extern ulong cpu_post_makecr (long v);
46 
47 static struct cpu_post_threex_s
48 {
49     ulong cmd;
50     ulong op1;
51     ulong op2;
52     ulong res;
53 } cpu_post_threex_table[] =
54 {
55     {
56 	OP_OR,
57 	0x1234,
58 	0x5678,
59 	0x1234 | 0x5678
60     },
61     {
62 	OP_ORC,
63 	0x1234,
64 	0x5678,
65 	0x1234 | ~0x5678
66     },
67     {
68 	OP_XOR,
69 	0x1234,
70 	0x5678,
71 	0x1234 ^ 0x5678
72     },
73     {
74 	OP_NAND,
75 	0x1234,
76 	0x5678,
77 	~(0x1234 & 0x5678)
78     },
79     {
80 	OP_NOR,
81 	0x1234,
82 	0x5678,
83 	~(0x1234 | 0x5678)
84     },
85     {
86 	OP_EQV,
87 	0x1234,
88 	0x5678,
89 	~(0x1234 ^ 0x5678)
90     },
91     {
92 	OP_SLW,
93 	0x80,
94 	16,
95 	0x800000
96     },
97     {
98 	OP_SLW,
99 	0x80,
100 	32,
101 	0
102     },
103     {
104 	OP_SRW,
105 	0x800000,
106 	16,
107 	0x80
108     },
109     {
110 	OP_SRW,
111 	0x800000,
112 	32,
113 	0
114     },
115     {
116 	OP_SRAW,
117 	0x80000000,
118 	3,
119 	0xf0000000
120     },
121     {
122 	OP_SRAW,
123 	0x8000,
124 	3,
125 	0x1000
126     },
127 };
128 static unsigned int cpu_post_threex_size = ARRAY_SIZE(cpu_post_threex_table);
129 
130 int cpu_post_test_threex (void)
131 {
132     int ret = 0;
133     unsigned int i, reg;
134     int flag = disable_interrupts();
135 
136     for (i = 0; i < cpu_post_threex_size && ret == 0; i++)
137     {
138 	struct cpu_post_threex_s *test = cpu_post_threex_table + i;
139 
140 	for (reg = 0; reg < 32 && ret == 0; reg++)
141 	{
142 	    unsigned int reg0 = (reg + 0) % 32;
143 	    unsigned int reg1 = (reg + 1) % 32;
144 	    unsigned int reg2 = (reg + 2) % 32;
145 	    unsigned int stk = reg < 16 ? 31 : 15;
146 	    unsigned long code[] =
147 	    {
148 		ASM_STW(stk, 1, -4),
149 		ASM_ADDI(stk, 1, -24),
150 		ASM_STW(3, stk, 12),
151 		ASM_STW(4, stk, 16),
152 		ASM_STW(reg0, stk, 8),
153 		ASM_STW(reg1, stk, 4),
154 		ASM_STW(reg2, stk, 0),
155 		ASM_LWZ(reg1, stk, 12),
156 		ASM_LWZ(reg0, stk, 16),
157 		ASM_12X(test->cmd, reg2, reg1, reg0),
158 		ASM_STW(reg2, stk, 12),
159 		ASM_LWZ(reg2, stk, 0),
160 		ASM_LWZ(reg1, stk, 4),
161 		ASM_LWZ(reg0, stk, 8),
162 		ASM_LWZ(3, stk, 12),
163 		ASM_ADDI(1, stk, 24),
164 		ASM_LWZ(stk, 1, -4),
165 		ASM_BLR,
166 	    };
167 	    unsigned long codecr[] =
168 	    {
169 		ASM_STW(stk, 1, -4),
170 		ASM_ADDI(stk, 1, -24),
171 		ASM_STW(3, stk, 12),
172 		ASM_STW(4, stk, 16),
173 		ASM_STW(reg0, stk, 8),
174 		ASM_STW(reg1, stk, 4),
175 		ASM_STW(reg2, stk, 0),
176 		ASM_LWZ(reg1, stk, 12),
177 		ASM_LWZ(reg0, stk, 16),
178 		ASM_12X(test->cmd, reg2, reg1, reg0) | BIT_C,
179 		ASM_STW(reg2, stk, 12),
180 		ASM_LWZ(reg2, stk, 0),
181 		ASM_LWZ(reg1, stk, 4),
182 		ASM_LWZ(reg0, stk, 8),
183 		ASM_LWZ(3, stk, 12),
184 		ASM_ADDI(1, stk, 24),
185 		ASM_LWZ(stk, 1, -4),
186 		ASM_BLR,
187 	    };
188 	    ulong res;
189 	    ulong cr;
190 
191 	    if (ret == 0)
192 	    {
193 		cr = 0;
194 		cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
195 
196 		ret = res == test->res && cr == 0 ? 0 : -1;
197 
198 		if (ret != 0)
199 		{
200 	            post_log ("Error at threex test %d !\n", i);
201 		}
202 	    }
203 
204 	    if (ret == 0)
205 	    {
206 		cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
207 
208 		ret = res == test->res &&
209 		      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
210 
211 		if (ret != 0)
212 		{
213 	            post_log ("Error at threex test %d !\n", i);
214 	        }
215 	    }
216 	}
217     }
218 
219     if (flag)
220 	enable_interrupts();
221 
222     return ret;
223 }
224 
225 #endif
226