1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 10 /* 11 * CPU test 12 * Shift instructions: srawi 13 * 14 * The test contains a pre-built table of instructions, operands and 15 * expected results. For each table entry, the test will cyclically use 16 * different sets of operand registers and result registers. 17 */ 18 19 #include <post.h> 20 #include "cpu_asm.h" 21 22 #if CONFIG_POST & CONFIG_SYS_POST_CPU 23 24 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); 25 extern ulong cpu_post_makecr (long v); 26 27 static struct cpu_post_srawi_s 28 { 29 ulong cmd; 30 ulong op1; 31 uchar op2; 32 ulong res; 33 } cpu_post_srawi_table[] = 34 { 35 { 36 OP_SRAWI, 37 0x8000, 38 3, 39 0x1000 40 }, 41 { 42 OP_SRAWI, 43 0x80000000, 44 3, 45 0xf0000000 46 }, 47 }; 48 static unsigned int cpu_post_srawi_size = ARRAY_SIZE(cpu_post_srawi_table); 49 50 int cpu_post_test_srawi (void) 51 { 52 int ret = 0; 53 unsigned int i, reg; 54 int flag = disable_interrupts(); 55 56 for (i = 0; i < cpu_post_srawi_size && ret == 0; i++) 57 { 58 struct cpu_post_srawi_s *test = cpu_post_srawi_table + i; 59 60 for (reg = 0; reg < 32 && ret == 0; reg++) 61 { 62 unsigned int reg0 = (reg + 0) % 32; 63 unsigned int reg1 = (reg + 1) % 32; 64 unsigned int stk = reg < 16 ? 31 : 15; 65 unsigned long code[] = 66 { 67 ASM_STW(stk, 1, -4), 68 ASM_ADDI(stk, 1, -16), 69 ASM_STW(3, stk, 8), 70 ASM_STW(reg0, stk, 4), 71 ASM_STW(reg1, stk, 0), 72 ASM_LWZ(reg0, stk, 8), 73 ASM_11S(test->cmd, reg1, reg0, test->op2), 74 ASM_STW(reg1, stk, 8), 75 ASM_LWZ(reg1, stk, 0), 76 ASM_LWZ(reg0, stk, 4), 77 ASM_LWZ(3, stk, 8), 78 ASM_ADDI(1, stk, 16), 79 ASM_LWZ(stk, 1, -4), 80 ASM_BLR, 81 }; 82 unsigned long codecr[] = 83 { 84 ASM_STW(stk, 1, -4), 85 ASM_ADDI(stk, 1, -16), 86 ASM_STW(3, stk, 8), 87 ASM_STW(reg0, stk, 4), 88 ASM_STW(reg1, stk, 0), 89 ASM_LWZ(reg0, stk, 8), 90 ASM_11S(test->cmd, reg1, reg0, test->op2) | BIT_C, 91 ASM_STW(reg1, stk, 8), 92 ASM_LWZ(reg1, stk, 0), 93 ASM_LWZ(reg0, stk, 4), 94 ASM_LWZ(3, stk, 8), 95 ASM_ADDI(1, stk, 16), 96 ASM_LWZ(stk, 1, -4), 97 ASM_BLR, 98 }; 99 ulong res; 100 ulong cr; 101 102 if (ret == 0) 103 { 104 cr = 0; 105 cpu_post_exec_21 (code, & cr, & res, test->op1); 106 107 ret = res == test->res && cr == 0 ? 0 : -1; 108 109 if (ret != 0) 110 { 111 post_log ("Error at srawi test %d !\n", i); 112 } 113 } 114 115 if (ret == 0) 116 { 117 cpu_post_exec_21 (codecr, & cr, & res, test->op1); 118 119 ret = res == test->res && 120 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; 121 122 if (ret != 0) 123 { 124 post_log ("Error at srawi test %d !\n", i); 125 } 126 } 127 } 128 } 129 130 if (flag) 131 enable_interrupts(); 132 133 return ret; 134 } 135 136 #endif 137