1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2002 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 #include <common.h> 8 9 /* 10 * CPU test 11 * Shift instructions: srawi 12 * 13 * The test contains a pre-built table of instructions, operands and 14 * expected results. For each table entry, the test will cyclically use 15 * different sets of operand registers and result registers. 16 */ 17 18 #include <post.h> 19 #include "cpu_asm.h" 20 21 #if CONFIG_POST & CONFIG_SYS_POST_CPU 22 23 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); 24 extern ulong cpu_post_makecr (long v); 25 26 static struct cpu_post_srawi_s 27 { 28 ulong cmd; 29 ulong op1; 30 uchar op2; 31 ulong res; 32 } cpu_post_srawi_table[] = 33 { 34 { 35 OP_SRAWI, 36 0x8000, 37 3, 38 0x1000 39 }, 40 { 41 OP_SRAWI, 42 0x80000000, 43 3, 44 0xf0000000 45 }, 46 }; 47 static unsigned int cpu_post_srawi_size = ARRAY_SIZE(cpu_post_srawi_table); 48 49 int cpu_post_test_srawi (void) 50 { 51 int ret = 0; 52 unsigned int i, reg; 53 int flag = disable_interrupts(); 54 55 for (i = 0; i < cpu_post_srawi_size && ret == 0; i++) 56 { 57 struct cpu_post_srawi_s *test = cpu_post_srawi_table + i; 58 59 for (reg = 0; reg < 32 && ret == 0; reg++) 60 { 61 unsigned int reg0 = (reg + 0) % 32; 62 unsigned int reg1 = (reg + 1) % 32; 63 unsigned int stk = reg < 16 ? 31 : 15; 64 unsigned long code[] = 65 { 66 ASM_STW(stk, 1, -4), 67 ASM_ADDI(stk, 1, -16), 68 ASM_STW(3, stk, 8), 69 ASM_STW(reg0, stk, 4), 70 ASM_STW(reg1, stk, 0), 71 ASM_LWZ(reg0, stk, 8), 72 ASM_11S(test->cmd, reg1, reg0, test->op2), 73 ASM_STW(reg1, stk, 8), 74 ASM_LWZ(reg1, stk, 0), 75 ASM_LWZ(reg0, stk, 4), 76 ASM_LWZ(3, stk, 8), 77 ASM_ADDI(1, stk, 16), 78 ASM_LWZ(stk, 1, -4), 79 ASM_BLR, 80 }; 81 unsigned long codecr[] = 82 { 83 ASM_STW(stk, 1, -4), 84 ASM_ADDI(stk, 1, -16), 85 ASM_STW(3, stk, 8), 86 ASM_STW(reg0, stk, 4), 87 ASM_STW(reg1, stk, 0), 88 ASM_LWZ(reg0, stk, 8), 89 ASM_11S(test->cmd, reg1, reg0, test->op2) | BIT_C, 90 ASM_STW(reg1, stk, 8), 91 ASM_LWZ(reg1, stk, 0), 92 ASM_LWZ(reg0, stk, 4), 93 ASM_LWZ(3, stk, 8), 94 ASM_ADDI(1, stk, 16), 95 ASM_LWZ(stk, 1, -4), 96 ASM_BLR, 97 }; 98 ulong res; 99 ulong cr; 100 101 if (ret == 0) 102 { 103 cr = 0; 104 cpu_post_exec_21 (code, & cr, & res, test->op1); 105 106 ret = res == test->res && cr == 0 ? 0 : -1; 107 108 if (ret != 0) 109 { 110 post_log ("Error at srawi test %d !\n", i); 111 } 112 } 113 114 if (ret == 0) 115 { 116 cpu_post_exec_21 (codecr, & cr, & res, test->op1); 117 118 ret = res == test->res && 119 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; 120 121 if (ret != 0) 122 { 123 post_log ("Error at srawi test %d !\n", i); 124 } 125 } 126 } 127 } 128 129 if (flag) 130 enable_interrupts(); 131 132 return ret; 133 } 134 135 #endif 136