1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2a47a12beSStefan Roese /* 3a47a12beSStefan Roese * (C) Copyright 2002 4a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5a47a12beSStefan Roese */ 6a47a12beSStefan Roese 7a47a12beSStefan Roese #include <common.h> 8a47a12beSStefan Roese 9a47a12beSStefan Roese /* 10a47a12beSStefan Roese * CPU test 11a47a12beSStefan Roese * Shift instructions: srawi 12a47a12beSStefan Roese * 13a47a12beSStefan Roese * The test contains a pre-built table of instructions, operands and 14a47a12beSStefan Roese * expected results. For each table entry, the test will cyclically use 15a47a12beSStefan Roese * different sets of operand registers and result registers. 16a47a12beSStefan Roese */ 17a47a12beSStefan Roese 18a47a12beSStefan Roese #include <post.h> 19a47a12beSStefan Roese #include "cpu_asm.h" 20a47a12beSStefan Roese 21a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU 22a47a12beSStefan Roese 23a47a12beSStefan Roese extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); 24a47a12beSStefan Roese extern ulong cpu_post_makecr (long v); 25a47a12beSStefan Roese 26a47a12beSStefan Roese static struct cpu_post_srawi_s 27a47a12beSStefan Roese { 28a47a12beSStefan Roese ulong cmd; 29a47a12beSStefan Roese ulong op1; 30a47a12beSStefan Roese uchar op2; 31a47a12beSStefan Roese ulong res; 32a47a12beSStefan Roese } cpu_post_srawi_table[] = 33a47a12beSStefan Roese { 34a47a12beSStefan Roese { 35a47a12beSStefan Roese OP_SRAWI, 36a47a12beSStefan Roese 0x8000, 37a47a12beSStefan Roese 3, 38a47a12beSStefan Roese 0x1000 39a47a12beSStefan Roese }, 40a47a12beSStefan Roese { 41a47a12beSStefan Roese OP_SRAWI, 42a47a12beSStefan Roese 0x80000000, 43a47a12beSStefan Roese 3, 44a47a12beSStefan Roese 0xf0000000 45a47a12beSStefan Roese }, 46a47a12beSStefan Roese }; 47d2397817SMike Frysinger static unsigned int cpu_post_srawi_size = ARRAY_SIZE(cpu_post_srawi_table); 48a47a12beSStefan Roese 49a47a12beSStefan Roese int cpu_post_test_srawi (void) 50a47a12beSStefan Roese { 51a47a12beSStefan Roese int ret = 0; 52a47a12beSStefan Roese unsigned int i, reg; 53a47a12beSStefan Roese int flag = disable_interrupts(); 54a47a12beSStefan Roese 55a47a12beSStefan Roese for (i = 0; i < cpu_post_srawi_size && ret == 0; i++) 56a47a12beSStefan Roese { 57a47a12beSStefan Roese struct cpu_post_srawi_s *test = cpu_post_srawi_table + i; 58a47a12beSStefan Roese 59a47a12beSStefan Roese for (reg = 0; reg < 32 && ret == 0; reg++) 60a47a12beSStefan Roese { 61a47a12beSStefan Roese unsigned int reg0 = (reg + 0) % 32; 62a47a12beSStefan Roese unsigned int reg1 = (reg + 1) % 32; 63a47a12beSStefan Roese unsigned int stk = reg < 16 ? 31 : 15; 64a47a12beSStefan Roese unsigned long code[] = 65a47a12beSStefan Roese { 66a47a12beSStefan Roese ASM_STW(stk, 1, -4), 67a47a12beSStefan Roese ASM_ADDI(stk, 1, -16), 68a47a12beSStefan Roese ASM_STW(3, stk, 8), 69a47a12beSStefan Roese ASM_STW(reg0, stk, 4), 70a47a12beSStefan Roese ASM_STW(reg1, stk, 0), 71a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8), 72a47a12beSStefan Roese ASM_11S(test->cmd, reg1, reg0, test->op2), 73a47a12beSStefan Roese ASM_STW(reg1, stk, 8), 74a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0), 75a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4), 76a47a12beSStefan Roese ASM_LWZ(3, stk, 8), 77a47a12beSStefan Roese ASM_ADDI(1, stk, 16), 78a47a12beSStefan Roese ASM_LWZ(stk, 1, -4), 79a47a12beSStefan Roese ASM_BLR, 80a47a12beSStefan Roese }; 81a47a12beSStefan Roese unsigned long codecr[] = 82a47a12beSStefan Roese { 83a47a12beSStefan Roese ASM_STW(stk, 1, -4), 84a47a12beSStefan Roese ASM_ADDI(stk, 1, -16), 85a47a12beSStefan Roese ASM_STW(3, stk, 8), 86a47a12beSStefan Roese ASM_STW(reg0, stk, 4), 87a47a12beSStefan Roese ASM_STW(reg1, stk, 0), 88a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8), 89a47a12beSStefan Roese ASM_11S(test->cmd, reg1, reg0, test->op2) | BIT_C, 90a47a12beSStefan Roese ASM_STW(reg1, stk, 8), 91a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0), 92a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4), 93a47a12beSStefan Roese ASM_LWZ(3, stk, 8), 94a47a12beSStefan Roese ASM_ADDI(1, stk, 16), 95a47a12beSStefan Roese ASM_LWZ(stk, 1, -4), 96a47a12beSStefan Roese ASM_BLR, 97a47a12beSStefan Roese }; 98a47a12beSStefan Roese ulong res; 99a47a12beSStefan Roese ulong cr; 100a47a12beSStefan Roese 101a47a12beSStefan Roese if (ret == 0) 102a47a12beSStefan Roese { 103a47a12beSStefan Roese cr = 0; 104a47a12beSStefan Roese cpu_post_exec_21 (code, & cr, & res, test->op1); 105a47a12beSStefan Roese 106a47a12beSStefan Roese ret = res == test->res && cr == 0 ? 0 : -1; 107a47a12beSStefan Roese 108a47a12beSStefan Roese if (ret != 0) 109a47a12beSStefan Roese { 110a47a12beSStefan Roese post_log ("Error at srawi test %d !\n", i); 111a47a12beSStefan Roese } 112a47a12beSStefan Roese } 113a47a12beSStefan Roese 114a47a12beSStefan Roese if (ret == 0) 115a47a12beSStefan Roese { 116a47a12beSStefan Roese cpu_post_exec_21 (codecr, & cr, & res, test->op1); 117a47a12beSStefan Roese 118a47a12beSStefan Roese ret = res == test->res && 119a47a12beSStefan Roese (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; 120a47a12beSStefan Roese 121a47a12beSStefan Roese if (ret != 0) 122a47a12beSStefan Roese { 123a47a12beSStefan Roese post_log ("Error at srawi test %d !\n", i); 124a47a12beSStefan Roese } 125a47a12beSStefan Roese } 126a47a12beSStefan Roese } 127a47a12beSStefan Roese } 128a47a12beSStefan Roese 129a47a12beSStefan Roese if (flag) 130a47a12beSStefan Roese enable_interrupts(); 131a47a12beSStefan Roese 132a47a12beSStefan Roese return ret; 133a47a12beSStefan Roese } 134a47a12beSStefan Roese 135a47a12beSStefan Roese #endif 136