1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 10 /* 11 * CPU test 12 * Shift instructions: rlwnm 13 * 14 * The test contains a pre-built table of instructions, operands and 15 * expected results. For each table entry, the test will cyclically use 16 * different sets of operand registers and result registers. 17 */ 18 19 #include <post.h> 20 #include "cpu_asm.h" 21 22 #if CONFIG_POST & CONFIG_SYS_POST_CPU 23 24 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, 25 ulong op2); 26 extern ulong cpu_post_makecr (long v); 27 28 static struct cpu_post_rlwnm_s 29 { 30 ulong cmd; 31 ulong op1; 32 ulong op2; 33 uchar mb; 34 uchar me; 35 ulong res; 36 } cpu_post_rlwnm_table[] = 37 { 38 { 39 OP_RLWNM, 40 0xffff0000, 41 24, 42 16, 43 23, 44 0x0000ff00 45 }, 46 }; 47 static unsigned int cpu_post_rlwnm_size = ARRAY_SIZE(cpu_post_rlwnm_table); 48 49 int cpu_post_test_rlwnm (void) 50 { 51 int ret = 0; 52 unsigned int i, reg; 53 int flag = disable_interrupts(); 54 55 for (i = 0; i < cpu_post_rlwnm_size && ret == 0; i++) 56 { 57 struct cpu_post_rlwnm_s *test = cpu_post_rlwnm_table + i; 58 59 for (reg = 0; reg < 32 && ret == 0; reg++) 60 { 61 unsigned int reg0 = (reg + 0) % 32; 62 unsigned int reg1 = (reg + 1) % 32; 63 unsigned int reg2 = (reg + 2) % 32; 64 unsigned int stk = reg < 16 ? 31 : 15; 65 unsigned long code[] = 66 { 67 ASM_STW(stk, 1, -4), 68 ASM_ADDI(stk, 1, -24), 69 ASM_STW(3, stk, 12), 70 ASM_STW(4, stk, 16), 71 ASM_STW(reg0, stk, 8), 72 ASM_STW(reg1, stk, 4), 73 ASM_STW(reg2, stk, 0), 74 ASM_LWZ(reg1, stk, 12), 75 ASM_LWZ(reg0, stk, 16), 76 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me), 77 ASM_STW(reg2, stk, 12), 78 ASM_LWZ(reg2, stk, 0), 79 ASM_LWZ(reg1, stk, 4), 80 ASM_LWZ(reg0, stk, 8), 81 ASM_LWZ(3, stk, 12), 82 ASM_ADDI(1, stk, 24), 83 ASM_LWZ(stk, 1, -4), 84 ASM_BLR, 85 }; 86 unsigned long codecr[] = 87 { 88 ASM_STW(stk, 1, -4), 89 ASM_ADDI(stk, 1, -24), 90 ASM_STW(3, stk, 12), 91 ASM_STW(4, stk, 16), 92 ASM_STW(reg0, stk, 8), 93 ASM_STW(reg1, stk, 4), 94 ASM_STW(reg2, stk, 0), 95 ASM_LWZ(reg1, stk, 12), 96 ASM_LWZ(reg0, stk, 16), 97 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) | 98 BIT_C, 99 ASM_STW(reg2, stk, 12), 100 ASM_LWZ(reg2, stk, 0), 101 ASM_LWZ(reg1, stk, 4), 102 ASM_LWZ(reg0, stk, 8), 103 ASM_LWZ(3, stk, 12), 104 ASM_ADDI(1, stk, 24), 105 ASM_LWZ(stk, 1, -4), 106 ASM_BLR, 107 }; 108 ulong res; 109 ulong cr; 110 111 if (ret == 0) 112 { 113 cr = 0; 114 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); 115 116 ret = res == test->res && cr == 0 ? 0 : -1; 117 118 if (ret != 0) 119 { 120 post_log ("Error at rlwnm test %d !\n", i); 121 } 122 } 123 124 if (ret == 0) 125 { 126 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); 127 128 ret = res == test->res && 129 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; 130 131 if (ret != 0) 132 { 133 post_log ("Error at rlwnm test %d !\n", i); 134 } 135 } 136 } 137 } 138 139 if (flag) 140 enable_interrupts(); 141 142 return ret; 143 } 144 145 #endif 146