1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 26 /* 27 * CPU test 28 * Shift instructions: rlwimi 29 * 30 * The test contains a pre-built table of instructions, operands and 31 * expected results. For each table entry, the test will cyclically use 32 * different sets of operand registers and result registers. 33 */ 34 35 #include <post.h> 36 #include "cpu_asm.h" 37 38 #if CONFIG_POST & CONFIG_SYS_POST_CPU 39 40 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, 41 ulong op2); 42 extern ulong cpu_post_makecr (long v); 43 44 static struct cpu_post_rlwimi_s 45 { 46 ulong cmd; 47 ulong op0; 48 ulong op1; 49 uchar op2; 50 uchar mb; 51 uchar me; 52 ulong res; 53 } cpu_post_rlwimi_table[] = 54 { 55 { 56 OP_RLWIMI, 57 0xff00ffff, 58 0x0000aa00, 59 8, 60 8, 61 15, 62 0xffaaffff 63 }, 64 }; 65 static unsigned int cpu_post_rlwimi_size = ARRAY_SIZE(cpu_post_rlwimi_table); 66 67 int cpu_post_test_rlwimi (void) 68 { 69 int ret = 0; 70 unsigned int i, reg; 71 int flag = disable_interrupts(); 72 73 for (i = 0; i < cpu_post_rlwimi_size && ret == 0; i++) 74 { 75 struct cpu_post_rlwimi_s *test = cpu_post_rlwimi_table + i; 76 77 for (reg = 0; reg < 32 && ret == 0; reg++) 78 { 79 unsigned int reg0 = (reg + 0) % 32; 80 unsigned int reg1 = (reg + 1) % 32; 81 unsigned int stk = reg < 16 ? 31 : 15; 82 unsigned long code[] = 83 { 84 ASM_STW(stk, 1, -4), 85 ASM_ADDI(stk, 1, -20), 86 ASM_STW(3, stk, 8), 87 ASM_STW(4, stk, 12), 88 ASM_STW(reg0, stk, 4), 89 ASM_STW(reg1, stk, 0), 90 ASM_LWZ(reg1, stk, 8), 91 ASM_LWZ(reg0, stk, 12), 92 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), 93 ASM_STW(reg1, stk, 8), 94 ASM_LWZ(reg1, stk, 0), 95 ASM_LWZ(reg0, stk, 4), 96 ASM_LWZ(3, stk, 8), 97 ASM_ADDI(1, stk, 20), 98 ASM_LWZ(stk, 1, -4), 99 ASM_BLR, 100 }; 101 unsigned long codecr[] = 102 { 103 ASM_STW(stk, 1, -4), 104 ASM_ADDI(stk, 1, -20), 105 ASM_STW(3, stk, 8), 106 ASM_STW(4, stk, 12), 107 ASM_STW(reg0, stk, 4), 108 ASM_STW(reg1, stk, 0), 109 ASM_LWZ(reg1, stk, 8), 110 ASM_LWZ(reg0, stk, 12), 111 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me) | 112 BIT_C, 113 ASM_STW(reg1, stk, 8), 114 ASM_LWZ(reg1, stk, 0), 115 ASM_LWZ(reg0, stk, 4), 116 ASM_LWZ(3, stk, 8), 117 ASM_ADDI(1, stk, 20), 118 ASM_LWZ(stk, 1, -4), 119 ASM_BLR, 120 }; 121 ulong res; 122 ulong cr; 123 124 if (ret == 0) 125 { 126 cr = 0; 127 cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1); 128 129 ret = res == test->res && cr == 0 ? 0 : -1; 130 131 if (ret != 0) 132 { 133 post_log ("Error at rlwimi test %d !\n", i); 134 } 135 } 136 137 if (ret == 0) 138 { 139 cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1); 140 141 ret = res == test->res && 142 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; 143 144 if (ret != 0) 145 { 146 post_log ("Error at rlwimi test %d !\n", i); 147 } 148 } 149 } 150 } 151 152 if (flag) 153 enable_interrupts(); 154 155 return ret; 156 } 157 158 #endif 159