1/* 2 * Copyright (C) 2002 Wolfgang Denk <wd@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#include <config.h> 8 9#include <post.h> 10#include <ppc_asm.tmpl> 11#include <ppc_defs.h> 12#include <asm/cache.h> 13 14#if CONFIG_POST & CONFIG_SYS_POST_CPU 15 16/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */ 17 .global cpu_post_exec_02 18cpu_post_exec_02: 19 isync 20 mflr r0 21 stwu r0, -4(r1) 22 23 subi r1, r1, 104 24 stmw r6, 0(r1) 25 26 mtlr r3 27 mr r3, r4 28 mr r4, r5 29 blrl 30 31 lmw r6, 0(r1) 32 addi r1, r1, 104 33 34 lwz r0, 0(r1) 35 addi r1, r1, 4 36 mtlr r0 37 blr 38 39/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */ 40 .global cpu_post_exec_04 41cpu_post_exec_04: 42 isync 43 mflr r0 44 stwu r0, -4(r1) 45 46 subi r1, r1, 96 47 stmw r8, 0(r1) 48 49 mtlr r3 50 mr r3, r4 51 mr r4, r5 52 mr r5, r6 53 mtxer r7 54 blrl 55 56 lmw r8, 0(r1) 57 addi r1, r1, 96 58 59 lwz r0, 0(r1) 60 addi r1, r1, 4 61 mtlr r0 62 blr 63 64/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */ 65 .global cpu_post_exec_12 66cpu_post_exec_12: 67 isync 68 mflr r0 69 stwu r0, -4(r1) 70 stwu r4, -4(r1) 71 72 mtlr r3 73 mr r3, r5 74 mr r4, r6 75 blrl 76 77 lwz r4, 0(r1) 78 stw r3, 0(r4) 79 80 lwz r0, 4(r1) 81 addi r1, r1, 8 82 mtlr r0 83 blr 84 85/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */ 86 .global cpu_post_exec_11 87cpu_post_exec_11: 88 isync 89 mflr r0 90 stwu r0, -4(r1) 91 stwu r4, -4(r1) 92 93 mtlr r3 94 mr r3, r5 95 blrl 96 97 lwz r4, 0(r1) 98 stw r3, 0(r4) 99 100 lwz r0, 4(r1) 101 addi r1, r1, 8 102 mtlr r0 103 blr 104 105/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */ 106 .global cpu_post_exec_21 107cpu_post_exec_21: 108 isync 109 mflr r0 110 stwu r0, -4(r1) 111 stwu r4, -4(r1) 112 stwu r5, -4(r1) 113 114 li r0, 0 115 mtxer r0 116 lwz r0, 0(r4) 117 mtcr r0 118 119 mtlr r3 120 mr r3, r6 121 blrl 122 123 mfcr r0 124 lwz r4, 4(r1) 125 stw r0, 0(r4) 126 lwz r4, 0(r1) 127 stw r3, 0(r4) 128 129 lwz r0, 8(r1) 130 addi r1, r1, 12 131 mtlr r0 132 blr 133 134/* void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, 135 ulong op2); */ 136 .global cpu_post_exec_22 137cpu_post_exec_22: 138 isync 139 mflr r0 140 stwu r0, -4(r1) 141 stwu r4, -4(r1) 142 stwu r5, -4(r1) 143 144 li r0, 0 145 mtxer r0 146 lwz r0, 0(r4) 147 mtcr r0 148 149 mtlr r3 150 mr r3, r6 151 mr r4, r7 152 blrl 153 154 mfcr r0 155 lwz r4, 4(r1) 156 stw r0, 0(r4) 157 lwz r4, 0(r1) 158 stw r3, 0(r4) 159 160 lwz r0, 8(r1) 161 addi r1, r1, 12 162 mtlr r0 163 blr 164 165/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */ 166 .global cpu_post_exec_12w 167cpu_post_exec_12w: 168 isync 169 mflr r0 170 stwu r0, -4(r1) 171 stwu r4, -4(r1) 172 173 mtlr r3 174 lwz r3, 0(r4) 175 mr r4, r5 176 mr r5, r6 177 blrl 178 179 lwz r4, 0(r1) 180 stw r3, 0(r4) 181 182 lwz r0, 4(r1) 183 addi r1, r1, 8 184 mtlr r0 185 blr 186 187/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */ 188 .global cpu_post_exec_11w 189cpu_post_exec_11w: 190 isync 191 mflr r0 192 stwu r0, -4(r1) 193 stwu r4, -4(r1) 194 195 mtlr r3 196 lwz r3, 0(r4) 197 mr r4, r5 198 blrl 199 200 lwz r4, 0(r1) 201 stw r3, 0(r4) 202 203 lwz r0, 4(r1) 204 addi r1, r1, 8 205 mtlr r0 206 blr 207 208/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */ 209 .global cpu_post_exec_22w 210cpu_post_exec_22w: 211 isync 212 mflr r0 213 stwu r0, -4(r1) 214 stwu r4, -4(r1) 215 stwu r6, -4(r1) 216 217 mtlr r3 218 lwz r3, 0(r4) 219 mr r4, r5 220 blrl 221 222 lwz r4, 4(r1) 223 stw r3, 0(r4) 224 lwz r4, 0(r1) 225 stw r5, 0(r4) 226 227 lwz r0, 8(r1) 228 addi r1, r1, 12 229 mtlr r0 230 blr 231 232/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */ 233 .global cpu_post_exec_21w 234cpu_post_exec_21w: 235 isync 236 mflr r0 237 stwu r0, -4(r1) 238 stwu r4, -4(r1) 239 stwu r5, -4(r1) 240 241 mtlr r3 242 lwz r3, 0(r4) 243 blrl 244 245 lwz r5, 4(r1) 246 stw r3, 0(r5) 247 lwz r5, 0(r1) 248 stw r4, 0(r5) 249 250 lwz r0, 8(r1) 251 addi r1, r1, 12 252 mtlr r0 253 blr 254 255/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */ 256 .global cpu_post_exec_21x 257cpu_post_exec_21x: 258 isync 259 mflr r0 260 stwu r0, -4(r1) 261 stwu r4, -4(r1) 262 stwu r5, -4(r1) 263 264 mtlr r3 265 mr r3, r6 266 blrl 267 268 lwz r5, 4(r1) 269 stw r3, 0(r5) 270 lwz r5, 0(r1) 271 stw r4, 0(r5) 272 273 lwz r0, 8(r1) 274 addi r1, r1, 12 275 mtlr r0 276 blr 277 278/* void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, 279 ulong cr); */ 280 .global cpu_post_exec_31 281cpu_post_exec_31: 282 isync 283 mflr r0 284 stwu r0, -4(r1) 285 stwu r4, -4(r1) 286 stwu r5, -4(r1) 287 stwu r6, -4(r1) 288 289 mtlr r3 290 lwz r3, 0(r4) 291 lwz r4, 0(r5) 292 mr r6, r7 293 294 mfcr r7 295 blrl 296 mtcr r7 297 298 lwz r7, 8(r1) 299 stw r3, 0(r7) 300 lwz r7, 4(r1) 301 stw r4, 0(r7) 302 lwz r7, 0(r1) 303 stw r5, 0(r7) 304 305 lwz r0, 12(r1) 306 addi r1, r1, 16 307 mtlr r0 308 blr 309 310/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */ 311 .global cpu_post_complex_1_asm 312cpu_post_complex_1_asm: 313 li r9,0 314 cmpw r9,r7 315 bge cpu_post_complex_1_done 316 mtctr r7 317cpu_post_complex_1_loop: 318 mullw r0,r3,r4 319 subf r0,r5,r0 320 divw r0,r0,r6 321 add r9,r9,r0 322 bdnz cpu_post_complex_1_loop 323cpu_post_complex_1_done: 324 mr r3,r9 325 blr 326 327/* int cpu_post_complex_2_asm (int x, int n); */ 328 .global cpu_post_complex_2_asm 329cpu_post_complex_2_asm: 330 mr. r0,r4 331 mtctr r0 332 mr r0,r3 333 li r3,1 334 li r4,1 335 blelr 336cpu_post_complex_2_loop: 337 mullw r3,r3,r0 338 add r3,r3,r4 339 bdnz cpu_post_complex_2_loop 340blr 341 342#endif 343