1/* 2 * Copyright (C) 2002 Wolfgang Denk <wd@denx.de> 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23#include <config.h> 24 25#include <post.h> 26#include <ppc_asm.tmpl> 27#include <ppc_defs.h> 28#include <asm/cache.h> 29 30#if CONFIG_POST & CONFIG_SYS_POST_CPU 31 32/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */ 33 .global cpu_post_exec_02 34cpu_post_exec_02: 35 isync 36 mflr r0 37 stwu r0, -4(r1) 38 39 subi r1, r1, 104 40 stmw r6, 0(r1) 41 42 mtlr r3 43 mr r3, r4 44 mr r4, r5 45 blrl 46 47 lmw r6, 0(r1) 48 addi r1, r1, 104 49 50 lwz r0, 0(r1) 51 addi r1, r1, 4 52 mtlr r0 53 blr 54 55/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */ 56 .global cpu_post_exec_04 57cpu_post_exec_04: 58 isync 59 mflr r0 60 stwu r0, -4(r1) 61 62 subi r1, r1, 96 63 stmw r8, 0(r1) 64 65 mtlr r3 66 mr r3, r4 67 mr r4, r5 68 mr r5, r6 69 mtxer r7 70 blrl 71 72 lmw r8, 0(r1) 73 addi r1, r1, 96 74 75 lwz r0, 0(r1) 76 addi r1, r1, 4 77 mtlr r0 78 blr 79 80/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */ 81 .global cpu_post_exec_12 82cpu_post_exec_12: 83 isync 84 mflr r0 85 stwu r0, -4(r1) 86 stwu r4, -4(r1) 87 88 mtlr r3 89 mr r3, r5 90 mr r4, r6 91 blrl 92 93 lwz r4, 0(r1) 94 stw r3, 0(r4) 95 96 lwz r0, 4(r1) 97 addi r1, r1, 8 98 mtlr r0 99 blr 100 101/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */ 102 .global cpu_post_exec_11 103cpu_post_exec_11: 104 isync 105 mflr r0 106 stwu r0, -4(r1) 107 stwu r4, -4(r1) 108 109 mtlr r3 110 mr r3, r5 111 blrl 112 113 lwz r4, 0(r1) 114 stw r3, 0(r4) 115 116 lwz r0, 4(r1) 117 addi r1, r1, 8 118 mtlr r0 119 blr 120 121/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */ 122 .global cpu_post_exec_21 123cpu_post_exec_21: 124 isync 125 mflr r0 126 stwu r0, -4(r1) 127 stwu r4, -4(r1) 128 stwu r5, -4(r1) 129 130 li r0, 0 131 mtxer r0 132 lwz r0, 0(r4) 133 mtcr r0 134 135 mtlr r3 136 mr r3, r6 137 blrl 138 139 mfcr r0 140 lwz r4, 4(r1) 141 stw r0, 0(r4) 142 lwz r4, 0(r1) 143 stw r3, 0(r4) 144 145 lwz r0, 8(r1) 146 addi r1, r1, 12 147 mtlr r0 148 blr 149 150/* void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, 151 ulong op2); */ 152 .global cpu_post_exec_22 153cpu_post_exec_22: 154 isync 155 mflr r0 156 stwu r0, -4(r1) 157 stwu r4, -4(r1) 158 stwu r5, -4(r1) 159 160 li r0, 0 161 mtxer r0 162 lwz r0, 0(r4) 163 mtcr r0 164 165 mtlr r3 166 mr r3, r6 167 mr r4, r7 168 blrl 169 170 mfcr r0 171 lwz r4, 4(r1) 172 stw r0, 0(r4) 173 lwz r4, 0(r1) 174 stw r3, 0(r4) 175 176 lwz r0, 8(r1) 177 addi r1, r1, 12 178 mtlr r0 179 blr 180 181/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */ 182 .global cpu_post_exec_12w 183cpu_post_exec_12w: 184 isync 185 mflr r0 186 stwu r0, -4(r1) 187 stwu r4, -4(r1) 188 189 mtlr r3 190 lwz r3, 0(r4) 191 mr r4, r5 192 mr r5, r6 193 blrl 194 195 lwz r4, 0(r1) 196 stw r3, 0(r4) 197 198 lwz r0, 4(r1) 199 addi r1, r1, 8 200 mtlr r0 201 blr 202 203/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */ 204 .global cpu_post_exec_11w 205cpu_post_exec_11w: 206 isync 207 mflr r0 208 stwu r0, -4(r1) 209 stwu r4, -4(r1) 210 211 mtlr r3 212 lwz r3, 0(r4) 213 mr r4, r5 214 blrl 215 216 lwz r4, 0(r1) 217 stw r3, 0(r4) 218 219 lwz r0, 4(r1) 220 addi r1, r1, 8 221 mtlr r0 222 blr 223 224/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */ 225 .global cpu_post_exec_22w 226cpu_post_exec_22w: 227 isync 228 mflr r0 229 stwu r0, -4(r1) 230 stwu r4, -4(r1) 231 stwu r6, -4(r1) 232 233 mtlr r3 234 lwz r3, 0(r4) 235 mr r4, r5 236 blrl 237 238 lwz r4, 4(r1) 239 stw r3, 0(r4) 240 lwz r4, 0(r1) 241 stw r5, 0(r4) 242 243 lwz r0, 8(r1) 244 addi r1, r1, 12 245 mtlr r0 246 blr 247 248/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */ 249 .global cpu_post_exec_21w 250cpu_post_exec_21w: 251 isync 252 mflr r0 253 stwu r0, -4(r1) 254 stwu r4, -4(r1) 255 stwu r5, -4(r1) 256 257 mtlr r3 258 lwz r3, 0(r4) 259 blrl 260 261 lwz r5, 4(r1) 262 stw r3, 0(r5) 263 lwz r5, 0(r1) 264 stw r4, 0(r5) 265 266 lwz r0, 8(r1) 267 addi r1, r1, 12 268 mtlr r0 269 blr 270 271/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */ 272 .global cpu_post_exec_21x 273cpu_post_exec_21x: 274 isync 275 mflr r0 276 stwu r0, -4(r1) 277 stwu r4, -4(r1) 278 stwu r5, -4(r1) 279 280 mtlr r3 281 mr r3, r6 282 blrl 283 284 lwz r5, 4(r1) 285 stw r3, 0(r5) 286 lwz r5, 0(r1) 287 stw r4, 0(r5) 288 289 lwz r0, 8(r1) 290 addi r1, r1, 12 291 mtlr r0 292 blr 293 294/* void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, 295 ulong cr); */ 296 .global cpu_post_exec_31 297cpu_post_exec_31: 298 isync 299 mflr r0 300 stwu r0, -4(r1) 301 stwu r4, -4(r1) 302 stwu r5, -4(r1) 303 stwu r6, -4(r1) 304 305 mtlr r3 306 lwz r3, 0(r4) 307 lwz r4, 0(r5) 308 mr r6, r7 309 310 mfcr r7 311 blrl 312 mtcr r7 313 314 lwz r7, 8(r1) 315 stw r3, 0(r7) 316 lwz r7, 4(r1) 317 stw r4, 0(r7) 318 lwz r7, 0(r1) 319 stw r5, 0(r7) 320 321 lwz r0, 12(r1) 322 addi r1, r1, 16 323 mtlr r0 324 blr 325 326/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */ 327 .global cpu_post_complex_1_asm 328cpu_post_complex_1_asm: 329 li r9,0 330 cmpw r9,r7 331 bge cpu_post_complex_1_done 332 mtctr r7 333cpu_post_complex_1_loop: 334 mullw r0,r3,r4 335 subf r0,r5,r0 336 divw r0,r0,r6 337 add r9,r9,r0 338 bdnz cpu_post_complex_1_loop 339cpu_post_complex_1_done: 340 mr r3,r9 341 blr 342 343/* int cpu_post_complex_2_asm (int x, int n); */ 344 .global cpu_post_complex_2_asm 345cpu_post_complex_2_asm: 346 mr. r0,r4 347 mtctr r0 348 mr r0,r3 349 li r3,1 350 li r4,1 351 blelr 352cpu_post_complex_2_loop: 353 mullw r3,r3,r0 354 add r3,r3,r4 355 bdnz cpu_post_complex_2_loop 356blr 357 358#endif 359