1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 10 /* 11 * CPU test 12 * Logic instructions: andi., andis. 13 * 14 * The test contains a pre-built table of instructions, operands and 15 * expected results. For each table entry, the test will cyclically use 16 * different sets of operand registers and result registers. 17 */ 18 19 #include <post.h> 20 #include "cpu_asm.h" 21 22 #if CONFIG_POST & CONFIG_SYS_POST_CPU 23 24 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); 25 extern ulong cpu_post_makecr (long v); 26 27 static struct cpu_post_andi_s 28 { 29 ulong cmd; 30 ulong op1; 31 ushort op2; 32 ulong res; 33 } cpu_post_andi_table[] = 34 { 35 { 36 OP_ANDI_, 37 0x80008000, 38 0xffff, 39 0x00008000 40 }, 41 { 42 OP_ANDIS_, 43 0x80008000, 44 0xffff, 45 0x80000000 46 }, 47 }; 48 static unsigned int cpu_post_andi_size = ARRAY_SIZE(cpu_post_andi_table); 49 50 int cpu_post_test_andi (void) 51 { 52 int ret = 0; 53 unsigned int i, reg; 54 int flag = disable_interrupts(); 55 56 for (i = 0; i < cpu_post_andi_size && ret == 0; i++) 57 { 58 struct cpu_post_andi_s *test = cpu_post_andi_table + i; 59 60 for (reg = 0; reg < 32 && ret == 0; reg++) 61 { 62 unsigned int reg0 = (reg + 0) % 32; 63 unsigned int reg1 = (reg + 1) % 32; 64 unsigned int stk = reg < 16 ? 31 : 15; 65 unsigned long codecr[] = 66 { 67 ASM_STW(stk, 1, -4), 68 ASM_ADDI(stk, 1, -16), 69 ASM_STW(3, stk, 8), 70 ASM_STW(reg0, stk, 4), 71 ASM_STW(reg1, stk, 0), 72 ASM_LWZ(reg0, stk, 8), 73 ASM_11IX(test->cmd, reg1, reg0, test->op2), 74 ASM_STW(reg1, stk, 8), 75 ASM_LWZ(reg1, stk, 0), 76 ASM_LWZ(reg0, stk, 4), 77 ASM_LWZ(3, stk, 8), 78 ASM_ADDI(1, stk, 16), 79 ASM_LWZ(stk, 1, -4), 80 ASM_BLR, 81 }; 82 ulong res; 83 ulong cr; 84 85 cpu_post_exec_21 (codecr, & cr, & res, test->op1); 86 87 ret = res == test->res && 88 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; 89 90 if (ret != 0) 91 { 92 post_log ("Error at andi test %d !\n", i); 93 } 94 } 95 } 96 97 if (flag) 98 enable_interrupts(); 99 100 return ret; 101 } 102 103 #endif 104