1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 26 /* 27 * CPU test 28 * Logic instructions: andi., andis. 29 * 30 * The test contains a pre-built table of instructions, operands and 31 * expected results. For each table entry, the test will cyclically use 32 * different sets of operand registers and result registers. 33 */ 34 35 #include <post.h> 36 #include "cpu_asm.h" 37 38 #if CONFIG_POST & CONFIG_SYS_POST_CPU 39 40 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); 41 extern ulong cpu_post_makecr (long v); 42 43 static struct cpu_post_andi_s 44 { 45 ulong cmd; 46 ulong op1; 47 ushort op2; 48 ulong res; 49 } cpu_post_andi_table[] = 50 { 51 { 52 OP_ANDI_, 53 0x80008000, 54 0xffff, 55 0x00008000 56 }, 57 { 58 OP_ANDIS_, 59 0x80008000, 60 0xffff, 61 0x80000000 62 }, 63 }; 64 static unsigned int cpu_post_andi_size = ARRAY_SIZE(cpu_post_andi_table); 65 66 int cpu_post_test_andi (void) 67 { 68 int ret = 0; 69 unsigned int i, reg; 70 int flag = disable_interrupts(); 71 72 for (i = 0; i < cpu_post_andi_size && ret == 0; i++) 73 { 74 struct cpu_post_andi_s *test = cpu_post_andi_table + i; 75 76 for (reg = 0; reg < 32 && ret == 0; reg++) 77 { 78 unsigned int reg0 = (reg + 0) % 32; 79 unsigned int reg1 = (reg + 1) % 32; 80 unsigned int stk = reg < 16 ? 31 : 15; 81 unsigned long codecr[] = 82 { 83 ASM_STW(stk, 1, -4), 84 ASM_ADDI(stk, 1, -16), 85 ASM_STW(3, stk, 8), 86 ASM_STW(reg0, stk, 4), 87 ASM_STW(reg1, stk, 0), 88 ASM_LWZ(reg0, stk, 8), 89 ASM_11IX(test->cmd, reg1, reg0, test->op2), 90 ASM_STW(reg1, stk, 8), 91 ASM_LWZ(reg1, stk, 0), 92 ASM_LWZ(reg0, stk, 4), 93 ASM_LWZ(3, stk, 8), 94 ASM_ADDI(1, stk, 16), 95 ASM_LWZ(stk, 1, -4), 96 ASM_BLR, 97 }; 98 ulong res; 99 ulong cr; 100 101 cpu_post_exec_21 (codecr, & cr, & res, test->op1); 102 103 ret = res == test->res && 104 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; 105 106 if (ret != 0) 107 { 108 post_log ("Error at andi test %d !\n", i); 109 } 110 } 111 } 112 113 if (flag) 114 enable_interrupts(); 115 116 return ret; 117 } 118 119 #endif 120