1 /* 2 * (C) Copyright 2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 #include <common.h> 25 26 /* Memory test 27 * 28 * General observations: 29 * o The recommended test sequence is to test the data lines: if they are 30 * broken, nothing else will work properly. Then test the address 31 * lines. Finally, test the cells in the memory now that the test 32 * program knows that the address and data lines work properly. 33 * This sequence also helps isolate and identify what is faulty. 34 * 35 * o For the address line test, it is a good idea to use the base 36 * address of the lowest memory location, which causes a '1' bit to 37 * walk through a field of zeros on the address lines and the highest 38 * memory location, which causes a '0' bit to walk through a field of 39 * '1's on the address line. 40 * 41 * o Floating buses can fool memory tests if the test routine writes 42 * a value and then reads it back immediately. The problem is, the 43 * write will charge the residual capacitance on the data bus so the 44 * bus retains its state briefely. When the test program reads the 45 * value back immediately, the capacitance of the bus can allow it 46 * to read back what was written, even though the memory circuitry 47 * is broken. To avoid this, the test program should write a test 48 * pattern to the target location, write a different pattern elsewhere 49 * to charge the residual capacitance in a differnt manner, then read 50 * the target location back. 51 * 52 * o Always read the target location EXACTLY ONCE and save it in a local 53 * variable. The problem with reading the target location more than 54 * once is that the second and subsequent reads may work properly, 55 * resulting in a failed test that tells the poor technician that 56 * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which 57 * doesn't help him one bit and causes puzzled phone calls. Been there, 58 * done that. 59 * 60 * Data line test: 61 * --------------- 62 * This tests data lines for shorts and opens by forcing adjacent data 63 * to opposite states. Because the data lines could be routed in an 64 * arbitrary manner the must ensure test patterns ensure that every case 65 * is tested. By using the following series of binary patterns every 66 * combination of adjacent bits is test regardless of routing. 67 * 68 * ...101010101010101010101010 69 * ...110011001100110011001100 70 * ...111100001111000011110000 71 * ...111111110000000011111111 72 * 73 * Carrying this out, gives us six hex patterns as follows: 74 * 75 * 0xaaaaaaaaaaaaaaaa 76 * 0xcccccccccccccccc 77 * 0xf0f0f0f0f0f0f0f0 78 * 0xff00ff00ff00ff00 79 * 0xffff0000ffff0000 80 * 0xffffffff00000000 81 * 82 * To test for short and opens to other signals on our boards, we 83 * simply test with the 1's complemnt of the paterns as well, resulting 84 * in twelve patterns total. 85 * 86 * After writing a test pattern. a special pattern 0x0123456789ABCDEF is 87 * written to a different address in case the data lines are floating. 88 * Thus, if a byte lane fails, you will see part of the special 89 * pattern in that byte lane when the test runs. For example, if the 90 * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa 91 * (for the 'a' test pattern). 92 * 93 * Address line test: 94 * ------------------ 95 * This function performs a test to verify that all the address lines 96 * hooked up to the RAM work properly. If there is an address line 97 * fault, it usually shows up as two different locations in the address 98 * map (related by the faulty address line) mapping to one physical 99 * memory storage location. The artifact that shows up is writing to 100 * the first location "changes" the second location. 101 * 102 * To test all address lines, we start with the given base address and 103 * xor the address with a '1' bit to flip one address line. For each 104 * test, we shift the '1' bit left to test the next address line. 105 * 106 * In the actual code, we start with address sizeof(ulong) since our 107 * test pattern we use is a ulong and thus, if we tried to test lower 108 * order address bits, it wouldn't work because our pattern would 109 * overwrite itself. 110 * 111 * Example for a 4 bit address space with the base at 0000: 112 * 0000 <- base 113 * 0001 <- test 1 114 * 0010 <- test 2 115 * 0100 <- test 3 116 * 1000 <- test 4 117 * Example for a 4 bit address space with the base at 0010: 118 * 0010 <- base 119 * 0011 <- test 1 120 * 0000 <- (below the base address, skipped) 121 * 0110 <- test 2 122 * 1010 <- test 3 123 * 124 * The test locations are successively tested to make sure that they are 125 * not "mirrored" onto the base address due to a faulty address line. 126 * Note that the base and each test location are related by one address 127 * line flipped. Note that the base address need not be all zeros. 128 * 129 * Memory tests 1-4: 130 * ----------------- 131 * These tests verify RAM using sequential writes and reads 132 * to/from RAM. There are several test cases that use different patterns to 133 * verify RAM. Each test case fills a region of RAM with one pattern and 134 * then reads the region back and compares its contents with the pattern. 135 * The following patterns are used: 136 * 137 * 1a) zero pattern (0x00000000) 138 * 1b) negative pattern (0xffffffff) 139 * 1c) checkerboard pattern (0x55555555) 140 * 1d) checkerboard pattern (0xaaaaaaaa) 141 * 2) bit-flip pattern ((1 << (offset % 32)) 142 * 3) address pattern (offset) 143 * 4) address pattern (~offset) 144 * 145 * Being run in normal mode, the test verifies only small 4Kb 146 * regions of RAM around each 1Mb boundary. For example, for 64Mb 147 * RAM the following areas are verified: 0x00000000-0x00000800, 148 * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800- 149 * 0x04000000. If the test is run in slow-test mode, it verifies 150 * the whole RAM. 151 */ 152 153 #ifdef CONFIG_POST 154 155 #include <post.h> 156 #include <watchdog.h> 157 158 #if CONFIG_POST & CFG_POST_MEMORY 159 160 DECLARE_GLOBAL_DATA_PTR; 161 162 /* 163 * Define INJECT_*_ERRORS for testing error detection in the presence of 164 * _good_ hardware. 165 */ 166 #undef INJECT_DATA_ERRORS 167 #undef INJECT_ADDRESS_ERRORS 168 169 #ifdef INJECT_DATA_ERRORS 170 #warning "Injecting data line errors for testing purposes" 171 #endif 172 173 #ifdef INJECT_ADDRESS_ERRORS 174 #warning "Injecting address line errors for testing purposes" 175 #endif 176 177 178 /* 179 * This function performs a double word move from the data at 180 * the source pointer to the location at the destination pointer. 181 * This is helpful for testing memory on processors which have a 64 bit 182 * wide data bus. 183 * 184 * On those PowerPC with FPU, use assembly and a floating point move: 185 * this does a 64 bit move. 186 * 187 * For other processors, let the compiler generate the best code it can. 188 */ 189 static void move64(unsigned long long *src, unsigned long long *dest) 190 { 191 #if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X) 192 asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ 193 "stfd 0, 0(4)" /* *dest = fpr0 */ 194 : : : "fr0" ); /* Clobbers fr0 */ 195 return; 196 #else 197 *dest = *src; 198 #endif 199 } 200 201 /* 202 * This is 64 bit wide test patterns. Note that they reside in ROM 203 * (which presumably works) and the tests write them to RAM which may 204 * not work. 205 * 206 * The "otherpattern" is written to drive the data bus to values other 207 * than the test pattern. This is for detecting floating bus lines. 208 * 209 */ 210 const static unsigned long long pattern[] = { 211 0xaaaaaaaaaaaaaaaaULL, 212 0xccccccccccccccccULL, 213 0xf0f0f0f0f0f0f0f0ULL, 214 0xff00ff00ff00ff00ULL, 215 0xffff0000ffff0000ULL, 216 0xffffffff00000000ULL, 217 0x00000000ffffffffULL, 218 0x0000ffff0000ffffULL, 219 0x00ff00ff00ff00ffULL, 220 0x0f0f0f0f0f0f0f0fULL, 221 0x3333333333333333ULL, 222 0x5555555555555555ULL 223 }; 224 const unsigned long long otherpattern = 0x0123456789abcdefULL; 225 226 227 static int memory_post_dataline(unsigned long long * pmem) 228 { 229 unsigned long long temp64 = 0; 230 int num_patterns = sizeof(pattern)/ sizeof(pattern[0]); 231 int i; 232 unsigned int hi, lo, pathi, patlo; 233 int ret = 0; 234 235 for ( i = 0; i < num_patterns; i++) { 236 move64((unsigned long long *)&(pattern[i]), pmem++); 237 /* 238 * Put a different pattern on the data lines: otherwise they 239 * may float long enough to read back what we wrote. 240 */ 241 move64((unsigned long long *)&otherpattern, pmem--); 242 move64(pmem, &temp64); 243 244 #ifdef INJECT_DATA_ERRORS 245 temp64 ^= 0x00008000; 246 #endif 247 248 if (temp64 != pattern[i]){ 249 pathi = (pattern[i]>>32) & 0xffffffff; 250 patlo = pattern[i] & 0xffffffff; 251 252 hi = (temp64>>32) & 0xffffffff; 253 lo = temp64 & 0xffffffff; 254 255 post_log ("Memory (date line) error at %08x, " 256 "wrote %08x%08x, read %08x%08x !\n", 257 pmem, pathi, patlo, hi, lo); 258 ret = -1; 259 } 260 } 261 return ret; 262 } 263 264 static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size) 265 { 266 ulong *target; 267 ulong *end; 268 ulong readback; 269 ulong xor; 270 int ret = 0; 271 272 end = (ulong *)((ulong)base + size); /* pointer arith! */ 273 xor = 0; 274 for(xor = sizeof(ulong); xor > 0; xor <<= 1) { 275 target = (ulong *)((ulong)testaddr ^ xor); 276 if((target >= base) && (target < end)) { 277 *testaddr = ~*target; 278 readback = *target; 279 280 #ifdef INJECT_ADDRESS_ERRORS 281 if(xor == 0x00008000) { 282 readback = *testaddr; 283 } 284 #endif 285 if(readback == *testaddr) { 286 post_log ("Memory (address line) error at %08x<->%08x, " 287 "XOR value %08x !\n", 288 testaddr, target, xor); 289 ret = -1; 290 } 291 } 292 } 293 return ret; 294 } 295 296 static int memory_post_test1 (unsigned long start, 297 unsigned long size, 298 unsigned long val) 299 { 300 unsigned long i; 301 ulong *mem = (ulong *) start; 302 ulong readback; 303 int ret = 0; 304 305 for (i = 0; i < size / sizeof (ulong); i++) { 306 mem[i] = val; 307 if (i % 1024 == 0) 308 WATCHDOG_RESET (); 309 } 310 311 for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { 312 readback = mem[i]; 313 if (readback != val) { 314 post_log ("Memory error at %08x, " 315 "wrote %08x, read %08x !\n", 316 mem + i, val, readback); 317 318 ret = -1; 319 break; 320 } 321 if (i % 1024 == 0) 322 WATCHDOG_RESET (); 323 } 324 325 return ret; 326 } 327 328 static int memory_post_test2 (unsigned long start, unsigned long size) 329 { 330 unsigned long i; 331 ulong *mem = (ulong *) start; 332 ulong readback; 333 int ret = 0; 334 335 for (i = 0; i < size / sizeof (ulong); i++) { 336 mem[i] = 1 << (i % 32); 337 if (i % 1024 == 0) 338 WATCHDOG_RESET (); 339 } 340 341 for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { 342 readback = mem[i]; 343 if (readback != (1 << (i % 32))) { 344 post_log ("Memory error at %08x, " 345 "wrote %08x, read %08x !\n", 346 mem + i, 1 << (i % 32), readback); 347 348 ret = -1; 349 break; 350 } 351 if (i % 1024 == 0) 352 WATCHDOG_RESET (); 353 } 354 355 return ret; 356 } 357 358 static int memory_post_test3 (unsigned long start, unsigned long size) 359 { 360 unsigned long i; 361 ulong *mem = (ulong *) start; 362 ulong readback; 363 int ret = 0; 364 365 for (i = 0; i < size / sizeof (ulong); i++) { 366 mem[i] = i; 367 if (i % 1024 == 0) 368 WATCHDOG_RESET (); 369 } 370 371 for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { 372 readback = mem[i]; 373 if (readback != i) { 374 post_log ("Memory error at %08x, " 375 "wrote %08x, read %08x !\n", 376 mem + i, i, readback); 377 378 ret = -1; 379 break; 380 } 381 if (i % 1024 == 0) 382 WATCHDOG_RESET (); 383 } 384 385 return ret; 386 } 387 388 static int memory_post_test4 (unsigned long start, unsigned long size) 389 { 390 unsigned long i; 391 ulong *mem = (ulong *) start; 392 ulong readback; 393 int ret = 0; 394 395 for (i = 0; i < size / sizeof (ulong); i++) { 396 mem[i] = ~i; 397 if (i % 1024 == 0) 398 WATCHDOG_RESET (); 399 } 400 401 for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { 402 readback = mem[i]; 403 if (readback != ~i) { 404 post_log ("Memory error at %08x, " 405 "wrote %08x, read %08x !\n", 406 mem + i, ~i, readback); 407 408 ret = -1; 409 break; 410 } 411 if (i % 1024 == 0) 412 WATCHDOG_RESET (); 413 } 414 415 return ret; 416 } 417 418 static int memory_post_tests (unsigned long start, unsigned long size) 419 { 420 int ret = 0; 421 422 if (ret == 0) 423 ret = memory_post_dataline ((unsigned long long *)start); 424 WATCHDOG_RESET (); 425 if (ret == 0) 426 ret = memory_post_addrline ((ulong *)start, (ulong *)start, size); 427 WATCHDOG_RESET (); 428 if (ret == 0) 429 ret = memory_post_addrline ((ulong *)(start + size - 8), 430 (ulong *)start, size); 431 WATCHDOG_RESET (); 432 if (ret == 0) 433 ret = memory_post_test1 (start, size, 0x00000000); 434 WATCHDOG_RESET (); 435 if (ret == 0) 436 ret = memory_post_test1 (start, size, 0xffffffff); 437 WATCHDOG_RESET (); 438 if (ret == 0) 439 ret = memory_post_test1 (start, size, 0x55555555); 440 WATCHDOG_RESET (); 441 if (ret == 0) 442 ret = memory_post_test1 (start, size, 0xaaaaaaaa); 443 WATCHDOG_RESET (); 444 if (ret == 0) 445 ret = memory_post_test2 (start, size); 446 WATCHDOG_RESET (); 447 if (ret == 0) 448 ret = memory_post_test3 (start, size); 449 WATCHDOG_RESET (); 450 if (ret == 0) 451 ret = memory_post_test4 (start, size); 452 WATCHDOG_RESET (); 453 454 return ret; 455 } 456 457 int memory_post_test (int flags) 458 { 459 int ret = 0; 460 bd_t *bd = gd->bd; 461 unsigned long memsize = (bd->bi_memsize >= 256 << 20 ? 462 256 << 20 : bd->bi_memsize) - (1 << 20); 463 464 465 if (flags & POST_SLOWTEST) { 466 ret = memory_post_tests (CFG_SDRAM_BASE, memsize); 467 } else { /* POST_NORMAL */ 468 469 unsigned long i; 470 471 for (i = 0; i < (memsize >> 20) && ret == 0; i++) { 472 if (ret == 0) 473 ret = memory_post_tests (i << 20, 0x800); 474 if (ret == 0) 475 ret = memory_post_tests ((i << 20) + 0xff800, 0x800); 476 } 477 } 478 479 return ret; 480 } 481 482 #endif /* CONFIG_POST & CFG_POST_MEMORY */ 483 #endif /* CONFIG_POST */ 484