1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2012-2013, Xilinx, Michal Simek 4 * 5 * (C) Copyright 2012 6 * Joe Hershberger <joe.hershberger@ni.com> 7 */ 8 9 #ifndef _ZYNQPL_H_ 10 #define _ZYNQPL_H_ 11 12 #include <xilinx.h> 13 14 #if defined(CONFIG_FPGA_ZYNQPL) 15 extern struct xilinx_fpga_op zynq_op; 16 # define FPGA_ZYNQPL_OPS &zynq_op 17 #else 18 # define FPGA_ZYNQPL_OPS NULL 19 #endif 20 21 #define XILINX_ZYNQ_7007S 0x3 22 #define XILINX_ZYNQ_7010 0x2 23 #define XILINX_ZYNQ_7012S 0x1c 24 #define XILINX_ZYNQ_7014S 0x8 25 #define XILINX_ZYNQ_7015 0x1b 26 #define XILINX_ZYNQ_7020 0x7 27 #define XILINX_ZYNQ_7030 0xc 28 #define XILINX_ZYNQ_7035 0x12 29 #define XILINX_ZYNQ_7045 0x11 30 #define XILINX_ZYNQ_7100 0x16 31 32 /* Device Image Sizes */ 33 #define XILINX_XC7Z007S_SIZE 16669920/8 34 #define XILINX_XC7Z010_SIZE 16669920/8 35 #define XILINX_XC7Z012S_SIZE 28085344/8 36 #define XILINX_XC7Z014S_SIZE 32364512/8 37 #define XILINX_XC7Z015_SIZE 28085344/8 38 #define XILINX_XC7Z020_SIZE 32364512/8 39 #define XILINX_XC7Z030_SIZE 47839328/8 40 #define XILINX_XC7Z035_SIZE 106571232/8 41 #define XILINX_XC7Z045_SIZE 106571232/8 42 #define XILINX_XC7Z100_SIZE 139330784/8 43 44 /* Descriptor Macros */ 45 #define XILINX_XC7Z007S_DESC(cookie) \ 46 { xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 47 "7z007s" } 48 49 #define XILINX_XC7Z010_DESC(cookie) \ 50 { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 51 "7z010" } 52 53 #define XILINX_XC7Z012S_DESC(cookie) \ 54 { xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 55 "7z012s" } 56 57 #define XILINX_XC7Z014S_DESC(cookie) \ 58 { xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 59 "7z014s" } 60 61 #define XILINX_XC7Z015_DESC(cookie) \ 62 { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 63 "7z015" } 64 65 #define XILINX_XC7Z020_DESC(cookie) \ 66 { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 67 "7z020" } 68 69 #define XILINX_XC7Z030_DESC(cookie) \ 70 { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 71 "7z030" } 72 73 #define XILINX_XC7Z035_DESC(cookie) \ 74 { xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 75 "7z035" } 76 77 #define XILINX_XC7Z045_DESC(cookie) \ 78 { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 79 "7z045" } 80 81 #define XILINX_XC7Z100_DESC(cookie) \ 82 { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \ 83 "7z100" } 84 85 #endif /* _ZYNQPL_H_ */ 86