183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2d5dae85fSMichal Simek /* 3d5dae85fSMichal Simek * (C) Copyright 2012-2013, Xilinx, Michal Simek 4d5dae85fSMichal Simek * 5d5dae85fSMichal Simek * (C) Copyright 2012 6d5dae85fSMichal Simek * Joe Hershberger <joe.hershberger@ni.com> 7d5dae85fSMichal Simek */ 8d5dae85fSMichal Simek 9d5dae85fSMichal Simek #ifndef _ZYNQPL_H_ 10d5dae85fSMichal Simek #define _ZYNQPL_H_ 11d5dae85fSMichal Simek 12d5dae85fSMichal Simek #include <xilinx.h> 13d5dae85fSMichal Simek 14*37e3a36aSSiva Durga Prasad Paladugu #ifdef CONFIG_CMD_ZYNQ_AES 15*37e3a36aSSiva Durga Prasad Paladugu int zynq_decrypt_load(u32 srcaddr, u32 dstaddr, u32 srclen, u32 dstlen); 16*37e3a36aSSiva Durga Prasad Paladugu #endif 17*37e3a36aSSiva Durga Prasad Paladugu 1814cfc4f3SMichal Simek extern struct xilinx_fpga_op zynq_op; 19d5dae85fSMichal Simek 204aba5fb8SMichal Simek #define XILINX_ZYNQ_XC7Z007S 0x3 214aba5fb8SMichal Simek #define XILINX_ZYNQ_XC7Z010 0x2 224aba5fb8SMichal Simek #define XILINX_ZYNQ_XC7Z012S 0x1c 234aba5fb8SMichal Simek #define XILINX_ZYNQ_XC7Z014S 0x8 244aba5fb8SMichal Simek #define XILINX_ZYNQ_XC7Z015 0x1b 254aba5fb8SMichal Simek #define XILINX_ZYNQ_XC7Z020 0x7 264aba5fb8SMichal Simek #define XILINX_ZYNQ_XC7Z030 0xc 274aba5fb8SMichal Simek #define XILINX_ZYNQ_XC7Z035 0x12 284aba5fb8SMichal Simek #define XILINX_ZYNQ_XC7Z045 0x11 294aba5fb8SMichal Simek #define XILINX_ZYNQ_XC7Z100 0x16 30d5dae85fSMichal Simek 31d5dae85fSMichal Simek /* Device Image Sizes */ 3205c59d0bSMichal Simek #define XILINX_XC7Z007S_SIZE 16669920/8 33d5dae85fSMichal Simek #define XILINX_XC7Z010_SIZE 16669920/8 3405c59d0bSMichal Simek #define XILINX_XC7Z012S_SIZE 28085344/8 3505c59d0bSMichal Simek #define XILINX_XC7Z014S_SIZE 32364512/8 3631993d6aSMichal Simek #define XILINX_XC7Z015_SIZE 28085344/8 37d5dae85fSMichal Simek #define XILINX_XC7Z020_SIZE 32364512/8 38d5dae85fSMichal Simek #define XILINX_XC7Z030_SIZE 47839328/8 39b9103809SSiva Durga Prasad Paladugu #define XILINX_XC7Z035_SIZE 106571232/8 40d5dae85fSMichal Simek #define XILINX_XC7Z045_SIZE 106571232/8 41fd2b10b6SMichal Simek #define XILINX_XC7Z100_SIZE 139330784/8 42d5dae85fSMichal Simek 434aba5fb8SMichal Simek /* Device Names */ 444aba5fb8SMichal Simek #define XILINX_XC7Z007S_NAME "7z007s" 454aba5fb8SMichal Simek #define XILINX_XC7Z010_NAME "7z010" 464aba5fb8SMichal Simek #define XILINX_XC7Z012S_NAME "7z012s" 474aba5fb8SMichal Simek #define XILINX_XC7Z014S_NAME "7z014s" 484aba5fb8SMichal Simek #define XILINX_XC7Z015_NAME "7z015" 494aba5fb8SMichal Simek #define XILINX_XC7Z020_NAME "7z020" 504aba5fb8SMichal Simek #define XILINX_XC7Z030_NAME "7z030" 514aba5fb8SMichal Simek #define XILINX_XC7Z035_NAME "7z035" 524aba5fb8SMichal Simek #define XILINX_XC7Z045_NAME "7z045" 534aba5fb8SMichal Simek #define XILINX_XC7Z100_NAME "7z100" 5405c59d0bSMichal Simek 554aba5fb8SMichal Simek #if defined(CONFIG_FPGA) 564aba5fb8SMichal Simek #define ZYNQ_DESC(name) { \ 574aba5fb8SMichal Simek .idcode = XILINX_ZYNQ_XC##name, \ 584aba5fb8SMichal Simek .fpga_size = XILINX_XC##name##_SIZE, \ 594aba5fb8SMichal Simek .devicename = XILINX_XC##name##_NAME \ 604aba5fb8SMichal Simek } 614aba5fb8SMichal Simek #else 624aba5fb8SMichal Simek #define ZYNQ_DESC(name) { \ 634aba5fb8SMichal Simek .idcode = XILINX_ZYNQ_XC##name, \ 644aba5fb8SMichal Simek .devicename = XILINX_XC##name##_NAME \ 654aba5fb8SMichal Simek } 664aba5fb8SMichal Simek #endif 67fd2b10b6SMichal Simek 68d5dae85fSMichal Simek #endif /* _ZYNQPL_H_ */ 69