1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Xilinx ZynqMP SoC Tap Delay Programming 4 * 5 * Copyright (C) 2018 Xilinx, Inc. 6 */ 7 8 #ifndef __ZYNQMP_TAP_DELAY_H__ 9 #define __ZYNQMP_TAP_DELAY_H__ 10 11 #ifdef CONFIG_ARCH_ZYNQMP 12 void zynqmp_dll_reset(u8 deviceid); 13 void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank); 14 #else 15 inline void zynqmp_dll_reset(u8 deviceid) {} 16 inline void arasan_zynqmp_set_tapdelay(u8 device_id, u8 uhsmode, u8 bank) {} 17 #endif 18 19 #endif 20