1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 285056932SStefan Roese /* 385056932SStefan Roese * Copyright (C) 2016 Stefan Roese <sr@denx.de> 485056932SStefan Roese */ 585056932SStefan Roese 685056932SStefan Roese #ifndef _WINBOND_W83627_H_ 785056932SStefan Roese #define _WINBOND_W83627_H_ 885056932SStefan Roese 985056932SStefan Roese /* I/O address of Winbond Super IO chip */ 1085056932SStefan Roese #define WINBOND_IO_PORT 0x2e 1185056932SStefan Roese 1285056932SStefan Roese /* Logical device number */ 1385056932SStefan Roese #define W83627DHG_FDC 0 /* Floppy */ 1485056932SStefan Roese #define W83627DHG_PP 1 /* Parallel port */ 1585056932SStefan Roese #define W83627DHG_SP1 2 /* Com1 */ 1685056932SStefan Roese #define W83627DHG_SP2 3 /* Com2 */ 1785056932SStefan Roese #define W83627DHG_KBC 5 /* PS/2 keyboard & mouse */ 1885056932SStefan Roese #define W83627DHG_SPI 6 /* Serial peripheral interface */ 1985056932SStefan Roese #define W83627DHG_WDTO_PLED 8 /* WDTO#, PLED */ 2085056932SStefan Roese #define W83627DHG_ACPI 10 /* ACPI */ 2185056932SStefan Roese #define W83627DHG_HWM 11 /* Hardware monitor */ 2285056932SStefan Roese #define W83627DHG_PECI_SST 12 /* PECI, SST */ 2385056932SStefan Roese 2485056932SStefan Roese /** 2585056932SStefan Roese * Configure the base I/O port of the specified serial device and enable the 2685056932SStefan Roese * serial device. 2785056932SStefan Roese * 2885056932SStefan Roese * @dev: high 8 bits = super I/O port, low 8 bits = logical device number 2985056932SStefan Roese * @iobase: processor I/O port address to assign to this serial device 3085056932SStefan Roese * @irq: processor IRQ number to assign to this serial device 3185056932SStefan Roese */ 3285056932SStefan Roese void winbond_enable_serial(uint dev, uint iobase, uint irq); 3385056932SStefan Roese 3485056932SStefan Roese #endif /* _WINBOND_W83627_H_ */ 35