1012771d8Swdenk /* 2012771d8Swdenk * (C) Copyright 2000 3012771d8Swdenk * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. 4012771d8Swdenk * 5012771d8Swdenk * See file CREDITS for list of people who contributed to this 6012771d8Swdenk * project. 7012771d8Swdenk * 8012771d8Swdenk * This program is free software; you can redistribute it and/or 9012771d8Swdenk * modify it under the terms of the GNU General Public License as 10012771d8Swdenk * published by the Free Software Foundation; either version 2 of 11012771d8Swdenk * the License, or (at your option) any later version. 12012771d8Swdenk * 13012771d8Swdenk * This program is distributed in the hope that it will be useful, 14012771d8Swdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 15012771d8Swdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16012771d8Swdenk * GNU General Public License for more details. 17012771d8Swdenk * 18012771d8Swdenk * You should have received a copy of the GNU General Public License 19012771d8Swdenk * along with this program; if not, write to the Free Software 20012771d8Swdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21012771d8Swdenk * MA 02111-1307 USA 22012771d8Swdenk */ 23012771d8Swdenk 24012771d8Swdenk /* winbond access routines and defines*/ 25012771d8Swdenk 26012771d8Swdenk /* from the winbond data sheet - 27012771d8Swdenk The W83C553F SIO controller with PCI arbiter is a multi-function PCI device. 28012771d8Swdenk Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller. 29012771d8Swdenk */ 30012771d8Swdenk 31012771d8Swdenk /*ISA bridge configuration space*/ 32012771d8Swdenk 33012771d8Swdenk #define W83C553F_VID 0x10AD 34012771d8Swdenk #define W83C553F_DID 0x0565 35012771d8Swdenk 36012771d8Swdenk #define WINBOND_PCICONTR 0x40 /*pci control reg*/ 37012771d8Swdenk #define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/ 38012771d8Swdenk #define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/ 39012771d8Swdenk #define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/ 40012771d8Swdenk #define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/ 41012771d8Swdenk #define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/ 42012771d8Swdenk #define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/ 43012771d8Swdenk #define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/ 44012771d8Swdenk #define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/ 45012771d8Swdenk #define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/ 46012771d8Swdenk #define WINBOND_CDR 0x4c /*Clock Divisor Register*/ 47012771d8Swdenk #define WINBOND_CSCR 0x4d /*Chip Select Control Register*/ 48012771d8Swdenk #define WINBOND_ATSCR 0x4e /*AT System Control register*/ 49012771d8Swdenk #define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/ 50012771d8Swdenk #define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/ 51012771d8Swdenk #define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/ 52012771d8Swdenk #define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/ 53012771d8Swdenk #define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/ 54012771d8Swdenk 55012771d8Swdenk #define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/ 56012771d8Swdenk 57012771d8Swdenk #define IPADCR_MBE512 0x1 58012771d8Swdenk #define IPADCR_MBE640 0x2 59012771d8Swdenk #define IPADCR_IPATOM4 0x10 60012771d8Swdenk #define IPADCR_IPATOM5 0x20 61012771d8Swdenk #define IPADCR_IPATOM6 0x40 62012771d8Swdenk #define IPADCR_IPATOM7 0x80 63012771d8Swdenk 64012771d8Swdenk #define CSCR_UBIOSCSE 0x10 65012771d8Swdenk #define CSCR_BIOSWP 0x20 66012771d8Swdenk 67012771d8Swdenk #define IDECSR_P0EN 0x01 68012771d8Swdenk #define IDECSR_P0F16 0x02 69012771d8Swdenk #define IDECSR_P1EN 0x10 70012771d8Swdenk #define IDECSR_P1F16 0x20 71012771d8Swdenk #define IDECSR_LEGIRQ 0x800 72012771d8Swdenk 73012771d8Swdenk /* 74012771d8Swdenk * Interrupt controller 75012771d8Swdenk */ 76*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_ICW1 CONFIG_SYS_ISA_IO + 0x20 77*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_ICW2 CONFIG_SYS_ISA_IO + 0x21 78*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_ICW3 CONFIG_SYS_ISA_IO + 0x21 79*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_ICW4 CONFIG_SYS_ISA_IO + 0x21 80*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_OCW1 CONFIG_SYS_ISA_IO + 0x21 81*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_OCW2 CONFIG_SYS_ISA_IO + 0x20 82*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_OCW3 CONFIG_SYS_ISA_IO + 0x20 83*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC1_ELC CONFIG_SYS_ISA_IO + 0x4D0 84*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_ICW1 CONFIG_SYS_ISA_IO + 0xA0 85*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_ICW2 CONFIG_SYS_ISA_IO + 0xA1 86*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_ICW3 CONFIG_SYS_ISA_IO + 0xA1 87*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_ICW4 CONFIG_SYS_ISA_IO + 0xA1 88*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_OCW1 CONFIG_SYS_ISA_IO + 0xA1 89*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_OCW2 CONFIG_SYS_ISA_IO + 0xA0 90*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_OCW3 CONFIG_SYS_ISA_IO + 0xA0 91*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_PIC2_ELC CONFIG_SYS_ISA_IO + 0x4D1 92012771d8Swdenk 93*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_TMR1_CMOD CONFIG_SYS_ISA_IO + 0x43 94012771d8Swdenk 95012771d8Swdenk /* 96012771d8Swdenk * DMA controller 97012771d8Swdenk */ 98*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_DMA1 CONFIG_SYS_ISA_IO + 0x000 /* channel 0 - 3 */ 99*6d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define W83C553F_DMA2 CONFIG_SYS_ISA_IO + 0x0C0 /* channel 4 - 7 */ 100012771d8Swdenk 101012771d8Swdenk /* command/status register bit definitions */ 102012771d8Swdenk 103012771d8Swdenk #define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */ 104012771d8Swdenk #define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */ 105012771d8Swdenk #define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */ 106012771d8Swdenk #define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */ 107012771d8Swdenk 108012771d8Swdenk #define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */ 109012771d8Swdenk #define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */ 110012771d8Swdenk #define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */ 111012771d8Swdenk #define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */ 112012771d8Swdenk 113012771d8Swdenk #define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */ 114012771d8Swdenk #define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */ 115012771d8Swdenk #define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */ 116012771d8Swdenk #define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */ 117012771d8Swdenk 118012771d8Swdenk /* mode register bit definitions */ 119012771d8Swdenk 120012771d8Swdenk #define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */ 121012771d8Swdenk #define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */ 122012771d8Swdenk #define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */ 123012771d8Swdenk #define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */ 124012771d8Swdenk #define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */ 125012771d8Swdenk #define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */ 126012771d8Swdenk #define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */ 127012771d8Swdenk #define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */ 128012771d8Swdenk #define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */ 129012771d8Swdenk #define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */ 130012771d8Swdenk #define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */ 131012771d8Swdenk #define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */ 132012771d8Swdenk #define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */ 133012771d8Swdenk #define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */ 134012771d8Swdenk 135012771d8Swdenk /* request register bit definitions */ 136012771d8Swdenk 137012771d8Swdenk #define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */ 138012771d8Swdenk #define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */ 139012771d8Swdenk #define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */ 140012771d8Swdenk #define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */ 141012771d8Swdenk #define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */ 142012771d8Swdenk 143012771d8Swdenk /* write single mask bit register bit definitions */ 144012771d8Swdenk 145012771d8Swdenk #define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */ 146012771d8Swdenk #define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */ 147012771d8Swdenk #define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */ 148012771d8Swdenk #define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */ 149012771d8Swdenk #define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */ 150012771d8Swdenk 151012771d8Swdenk /* read/write all mask bits register bit definitions */ 152012771d8Swdenk 153012771d8Swdenk #define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */ 154012771d8Swdenk #define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */ 155012771d8Swdenk #define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */ 156012771d8Swdenk #define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */ 157012771d8Swdenk 158012771d8Swdenk /* typedefs */ 159012771d8Swdenk 160012771d8Swdenk #define W83C553F_DMA1_CS 0x8 161012771d8Swdenk #define W83C553F_DMA1_WR 0x9 162012771d8Swdenk #define W83C553F_DMA1_WSMB 0xA 163012771d8Swdenk #define W83C553F_DMA1_WM 0xB 164012771d8Swdenk #define W83C553F_DMA1_CBP 0xC 165012771d8Swdenk #define W83C553F_DMA1_MC 0xD 166012771d8Swdenk #define W83C553F_DMA1_CM 0xE 167012771d8Swdenk #define W83C553F_DMA1_RWAMB 0xF 168012771d8Swdenk 169012771d8Swdenk #define W83C553F_DMA2_CS 0x10 170012771d8Swdenk #define W83C553F_DMA2_WR 0x12 171012771d8Swdenk #define W83C553F_DMA2_WSMB 0x14 172012771d8Swdenk #define W83C553F_DMA2_WM 0x16 173012771d8Swdenk #define W83C553F_DMA2_CBP 0x18 174012771d8Swdenk #define W83C553F_DMA2_MC 0x1A 175012771d8Swdenk #define W83C553F_DMA2_CM 0x1C 176012771d8Swdenk #define W83C553F_DMA2_RWAMB 0x1E 177012771d8Swdenk 178012771d8Swdenk void initialise_w83c553f(void); 179