xref: /openbmc/u-boot/include/vsc9953.h (revision ee7bb5be) 
1 /*
2  * Copyright 2013, 2015 Freescale Semiconductor, Inc.
3  *
4  * SPDX-License-Identifier:      GPL-2.0+
5  *
6  * Driver for the Vitesse VSC9953 L2 Switch
7  */
8 
9 #ifndef _VSC9953_H_
10 #define _VSC9953_H_
11 
12 #include <config.h>
13 #include <miiphy.h>
14 #include <asm/types.h>
15 
16 #define VSC9953_OFFSET			(CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
17 
18 #define VSC9953_SYS_OFFSET		0x010000
19 #define VSC9953_REW_OFFSET		0x030000
20 #define VSC9953_DEV_GMII_OFFSET		0x100000
21 #define VSC9953_QSYS_OFFSET		0x200000
22 #define VSC9953_ANA_OFFSET		0x280000
23 #define VSC9953_DEVCPU_GCB		0x070000
24 #define VSC9953_ES0			0x040000
25 #define VSC9953_IS1			0x050000
26 #define VSC9953_IS2			0x060000
27 
28 #define T1040_SWITCH_GMII_DEV_OFFSET	0x010000
29 #define VSC9953_PHY_REGS_OFFST		0x0000AC
30 
31 /* Macros for vsc9953_chip_regs.soft_rst register */
32 #define VSC9953_SOFT_SWC_RST_ENA	0x00000001
33 
34 /* Macros for vsc9953_sys_sys.reset_cfg register */
35 #define VSC9953_CORE_ENABLE		0x80
36 #define VSC9953_MEM_ENABLE		0x40
37 #define VSC9953_MEM_INIT		0x20
38 
39 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
40 #define VSC9953_MAC_ENA_CFG		0x00000011
41 
42 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
43 #define VSC9953_MAC_MODE_CFG		0x00000011
44 
45 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
46 #define VSC9953_MAC_IFG_CFG		0x00000515
47 
48 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
49 #define VSC9953_MAC_HDX_CFG		0x00001043
50 
51 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
52 #define VSC9953_MAC_MAX_LEN		0x000005ee
53 
54 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
55 #define VSC9953_CLOCK_CFG		0x00000001
56 #define VSC9953_CLOCK_CFG_1000M		0x00000001
57 
58 /* Macros for vsc9953_sys_sys.front_port_mode register */
59 #define VSC9953_FRONT_PORT_MODE	0x00000000
60 
61 /* Macros for vsc9953_ana_pfc.pfc_cfg register */
62 #define VSC9953_PFC_FC			0x00000001
63 #define VSC9953_PFC_FC_QSGMII		0x00000000
64 
65 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
66 #define VSC9953_MAC_FC_CFG		0x04700000
67 #define VSC9953_MAC_FC_CFG_QSGMII	0x00700000
68 
69 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
70 #define VSC9953_PAUSE_CFG		0x001ffffe
71 
72 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
73 #define VSC9953_TOT_TAIL_DROP_LVL	0x000003ff
74 
75 /* Macros for vsc9953_sys_sys.stat_cfg register */
76 #define VSC9953_STAT_CLEAR_RX		0x00000400
77 #define VSC9953_STAT_CLEAR_TX		0x00000800
78 #define VSC9953_STAT_CLEAR_DR		0x00001000
79 
80 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
81 #define VSC9953_VCAP_MV_CFG		0x0000ffff
82 #define VSC9953_VCAP_UPDATE_CTRL	0x01000004
83 
84 /* Macros for register vsc9953_ana_ana_tables.mac_access register */
85 #define VSC9953_MAC_CMD_IDLE		0x00000000
86 #define VSC9953_MAC_CMD_LEARN		0x00000001
87 #define VSC9953_MAC_CMD_FORGET		0x00000002
88 #define VSC9953_MAC_CMD_AGE		0x00000003
89 #define VSC9953_MAC_CMD_NEXT		0x00000004
90 #define VSC9953_MAC_CMD_READ		0x00000006
91 #define VSC9953_MAC_CMD_WRITE		0x00000007
92 #define VSC9953_MAC_CMD_MASK		0x00000007
93 #define VSC9953_MAC_CMD_VALID		0x00000800
94 #define VSC9953_MAC_ENTRYTYPE_NORMAL	0x00000000
95 #define VSC9953_MAC_ENTRYTYPE_LOCKED	0x00000200
96 #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST	0x00000400
97 #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST	0x00000600
98 #define VSC9953_MAC_ENTRYTYPE_MASK	0x00000600
99 #define VSC9953_MAC_DESTIDX_MASK	0x000001f8
100 #define VSC9953_MAC_VID_MASK		0x1fff0000
101 #define VSC9953_MAC_MACH_MASK		0x0000ffff
102 
103 /* Macros for vsc9953_ana_port.vlan_cfg register */
104 #define VSC9953_VLAN_CFG_AWARE_ENA	0x00100000
105 #define VSC9953_VLAN_CFG_POP_CNT_MASK	0x000c0000
106 #define VSC9953_VLAN_CFG_POP_CNT_NONE	0x00000000
107 #define VSC9953_VLAN_CFG_POP_CNT_ONE	0x00040000
108 #define VSC9953_VLAN_CFG_VID_MASK	0x00000fff
109 
110 /* Macros for vsc9953_rew_port.port_vlan_cfg register */
111 #define VSC9953_PORT_VLAN_CFG_VID_MASK	0x00000fff
112 
113 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
114 #define VSC9953_ANA_TBL_VID_MASK	0x00000fff
115 
116 /* Macros for vsc9953_ana_ana_tables.vlan_access register */
117 #define VSC9953_VLAN_PORT_MASK		0x00001ffc
118 #define VSC9953_VLAN_CMD_MASK		0x00000003
119 #define VSC9953_VLAN_CMD_IDLE		0x00000000
120 #define VSC9953_VLAN_CMD_READ		0x00000001
121 #define VSC9953_VLAN_CMD_WRITE		0x00000002
122 #define VSC9953_VLAN_CMD_INIT		0x00000003
123 
124 /* Macros for vsc9953_ana_port.port_cfg register */
125 #define VSC9953_PORT_CFG_LEARN_ENA	0x00000080
126 #define VSC9953_PORT_CFG_LEARN_AUTO	0x00000100
127 #define VSC9953_PORT_CFG_LEARN_CPU	0x00000200
128 #define VSC9953_PORT_CFG_LEARN_DROP	0x00000400
129 #define VSC9953_PORT_CFG_PORTID_MASK	0x0000003c
130 
131 /* Macros for vsc9953_qsys_sys.switch_port_mode register */
132 #define VSC9953_PORT_ENA		0x00002000
133 
134 /* Macros for vsc9953_ana_ana.agen_ctrl register */
135 #define VSC9953_FID_MASK_ALL		0x00fff000
136 
137 /* Macros for vsc9953_ana_ana.adv_learn register */
138 #define VSC9953_VLAN_CHK		0x00000400
139 
140 /* Macros for vsc9953_ana_ana.auto_age register */
141 #define VSC9953_AUTOAGE_PERIOD_MASK	0x001ffffe
142 
143 /* Macros for vsc9953_rew_port.port_tag_cfg register */
144 #define VSC9953_TAG_CFG_MASK		0x00000180
145 #define VSC9953_TAG_CFG_NONE		0x00000000
146 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO	0x00000080
147 #define VSC9953_TAG_CFG_ALL_BUT_ZERO		0x00000100
148 #define VSC9953_TAG_CFG_ALL		0x00000180
149 #define VSC9953_TAG_VID_PVID		0x00000010
150 
151 /* Macros for vsc9953_ana_ana.anag_efil register */
152 #define VSC9953_AGE_PORT_EN		0x00080000
153 #define VSC9953_AGE_PORT_MASK		0x0007c000
154 #define VSC9953_AGE_VID_EN		0x00002000
155 #define VSC9953_AGE_VID_MASK		0x00001fff
156 
157 /* Macros for vsc9953_ana_ana_tables.mach_data register */
158 #define VSC9953_MACHDATA_VID_MASK	0x1fff0000
159 
160 /* Macros for vsc9953_ana_common.aggr_cfg register */
161 #define VSC9953_AC_RND_ENA		0x00000080
162 #define VSC9953_AC_DMAC_ENA		0x00000040
163 #define VSC9953_AC_SMAC_ENA		0x00000020
164 #define VSC9953_AC_IP6_LBL_ENA		0x00000010
165 #define VSC9953_AC_IP6_TCPUDP_ENA	0x00000008
166 #define VSC9953_AC_IP4_SIPDIP_ENA	0x00000004
167 #define VSC9953_AC_IP4_TCPUDP_ENA	0x00000002
168 #define VSC9953_AC_MASK			0x000000fe
169 
170 /* Macros for vsc9953_ana_pgid.port_grp_id[] registers */
171 #define VSC9953_PGID_PORT_MASK		0x000003ff
172 
173 #define VSC9953_MAX_PORTS		10
174 #define VSC9953_PORT_CHECK(port)	\
175 	(((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
176 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \
177 	( \
178 		(port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
179 	) ? 0 : 1 \
180 )
181 #define VSC9953_MAX_VLAN		4096
182 #define VSC9953_VLAN_CHECK(vid)	\
183 	(((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
184 #define VSC9953_DEFAULT_AGE_TIME	300
185 
186 #define DEFAULT_VSC9953_MDIO_NAME	"VSC9953_MDIO0"
187 
188 #define MIIMIND_OPR_PEND		0x00000004
189 
190 struct vsc9953_mdio_info {
191 	struct vsc9953_mii_mng	*regs;
192 	char	*name;
193 };
194 
195 /* VSC9953 ANA structure */
196 
197 struct vsc9953_ana_port {
198 	u32	vlan_cfg;
199 	u32	drop_cfg;
200 	u32	qos_cfg;
201 	u32	vcap_cfg;
202 	u32	vcap_s1_key_cfg[3];
203 	u32	vcap_s2_cfg;
204 	u32	qos_pcp_dei_map_cfg[16];
205 	u32	cpu_fwd_cfg;
206 	u32	cpu_fwd_bpdu_cfg;
207 	u32	cpu_fwd_garp_cfg;
208 	u32	cpu_fwd_ccm_cfg;
209 	u32	port_cfg;
210 	u32	pol_cfg;
211 	u32	reserved[34];
212 };
213 
214 struct vsc9953_ana_pol {
215 	u32	pol_pir_cfg;
216 	u32	pol_cir_cfg;
217 	u32	pol_mode_cfg;
218 	u32	pol_pir_state;
219 	u32	pol_cir_state;
220 	u32	reserved1[3];
221 };
222 
223 struct vsc9953_ana_ana_tables {
224 	u32	entry_lim[11];
225 	u32	an_moved;
226 	u32	mach_data;
227 	u32	macl_data;
228 	u32	mac_access;
229 	u32	mact_indx;
230 	u32	vlan_access;
231 	u32	vlan_tidx;
232 };
233 
234 struct vsc9953_ana_ana {
235 	u32	adv_learn;
236 	u32	vlan_mask;
237 	u32	reserved;
238 	u32	anag_efil;
239 	u32	an_events;
240 	u32	storm_limit_burst;
241 	u32	storm_limit_cfg[4];
242 	u32	isolated_prts;
243 	u32	community_ports;
244 	u32	auto_age;
245 	u32	mac_options;
246 	u32	learn_disc;
247 	u32	agen_ctrl;
248 	u32	mirror_ports;
249 	u32	emirror_ports;
250 	u32	flooding;
251 	u32	flooding_ipmc;
252 	u32	sflow_cfg[11];
253 	u32	port_mode[12];
254 };
255 
256 #define PGID_DST_START		0
257 #define PGID_AGGR_START		64
258 #define PGID_SRC_START		80
259 
260 struct vsc9953_ana_pgid {
261 	u32	port_grp_id[91];
262 };
263 
264 struct vsc9953_ana_pfc {
265 	u32	pfc_cfg;
266 	u32	reserved1[15];
267 };
268 
269 struct vsc9953_ana_pol_misc {
270 	u32	pol_flowc[10];
271 	u32	reserved1[17];
272 	u32	pol_hyst;
273 };
274 
275 struct vsc9953_ana_common {
276 	u32	aggr_cfg;
277 	u32	cpuq_cfg;
278 	u32	cpuq_8021_cfg;
279 	u32	dscp_cfg;
280 	u32	dscp_rewr_cfg;
281 	u32	vcap_rng_type_cfg;
282 	u32	vcap_rng_val_cfg;
283 	u32	discard_cfg;
284 	u32	fid_cfg;
285 };
286 
287 struct vsc9953_analyzer {
288 	struct vsc9953_ana_port	port[11];
289 	u32	reserved1[9536];
290 	struct vsc9953_ana_pol	pol[164];
291 	struct vsc9953_ana_ana_tables	ana_tables;
292 	u32	reserved2[14];
293 	struct vsc9953_ana_ana	ana;
294 	u32	reserved3[21];
295 	struct vsc9953_ana_pgid	port_id_tbl;
296 	u32	reserved4[549];
297 	struct vsc9953_ana_pfc	pfc[10];
298 	struct vsc9953_ana_pol_misc	pol_misc;
299 	u32	reserved5[196];
300 	struct vsc9953_ana_common	common;
301 };
302 /* END VSC9953 ANA structure t*/
303 
304 /* VSC9953 DEV_GMII structure */
305 
306 struct vsc9953_dev_gmii_port_mode {
307 	u32	clock_cfg;
308 	u32	port_misc;
309 	u32	reserved1;
310 	u32	eee_cfg;
311 };
312 
313 struct vsc9953_dev_gmii_mac_cfg_status {
314 	u32	mac_ena_cfg;
315 	u32	mac_mode_cfg;
316 	u32	mac_maxlen_cfg;
317 	u32	mac_tags_cfg;
318 	u32	mac_adv_chk_cfg;
319 	u32	mac_ifg_cfg;
320 	u32	mac_hdx_cfg;
321 	u32	mac_fc_mac_low_cfg;
322 	u32	mac_fc_mac_high_cfg;
323 	u32	mac_sticky;
324 };
325 
326 struct vsc9953_dev_gmii {
327 	struct vsc9953_dev_gmii_port_mode	port_mode;
328 	struct vsc9953_dev_gmii_mac_cfg_status	mac_cfg_status;
329 };
330 
331 /* END VSC9953 DEV_GMII structure */
332 
333 /* VSC9953 QSYS structure */
334 
335 struct vsc9953_qsys_hsch {
336 	u32	cir_cfg;
337 	u32	reserved1;
338 	u32	se_cfg;
339 	u32	se_dwrr_cfg[8];
340 	u32	cir_state;
341 	u32	reserved2[20];
342 };
343 
344 struct vsc9953_qsys_sys {
345 	u32	port_mode[12];
346 	u32	switch_port_mode[11];
347 	u32	stat_cnt_cfg;
348 	u32	eee_cfg[10];
349 	u32	eee_thrs;
350 	u32	igr_no_sharing;
351 	u32	egr_no_sharing;
352 	u32	sw_status[11];
353 	u32	ext_cpu_cfg;
354 	u32	cpu_group_map;
355 	u32	reserved1[23];
356 };
357 
358 struct vsc9953_qsys_qos_cfg {
359 	u32	red_profile[16];
360 	u32	res_qos_mode;
361 };
362 
363 struct vsc9953_qsys_drop_cfg {
364 	u32	egr_drop_mode;
365 };
366 
367 struct vsc9953_qsys_mmgt {
368 	u32	eq_cntrl;
369 	u32	reserved1;
370 };
371 
372 struct vsc9953_qsys_hsch_misc {
373 	u32	hsch_misc_cfg;
374 	u32	reserved1[546];
375 };
376 
377 struct vsc9953_qsys_res_ctrl {
378 	u32	res_cfg;
379 	u32	res_stat;
380 
381 };
382 
383 struct vsc9953_qsys_reg {
384 	struct vsc9953_qsys_hsch	hsch[108];
385 	struct vsc9953_qsys_sys	sys;
386 	struct vsc9953_qsys_qos_cfg	qos_cfg;
387 	struct vsc9953_qsys_drop_cfg	drop_cfg;
388 	struct vsc9953_qsys_mmgt	mmgt;
389 	struct vsc9953_qsys_hsch_misc	hsch_misc;
390 	struct vsc9953_qsys_res_ctrl	res_ctrl[1024];
391 };
392 
393 /* END VSC9953 QSYS structure */
394 
395 /* VSC9953 SYS structure */
396 
397 struct vsc9953_rx_cntrs {
398 	u32	c_rx_oct;
399 	u32	c_rx_uc;
400 	u32	c_rx_mc;
401 	u32	c_rx_bc;
402 	u32	c_rx_short;
403 	u32	c_rx_frag;
404 	u32	c_rx_jabber;
405 	u32	c_rx_crc;
406 	u32	c_rx_symbol_err;
407 	u32	c_rx_sz_64;
408 	u32	c_rx_sz_65_127;
409 	u32	c_rx_sz_128_255;
410 	u32	c_rx_sz_256_511;
411 	u32	c_rx_sz_512_1023;
412 	u32	c_rx_sz_1024_1526;
413 	u32	c_rx_sz_jumbo;
414 	u32	c_rx_pause;
415 	u32	c_rx_control;
416 	u32	c_rx_long;
417 	u32	c_rx_cat_drop;
418 	u32	c_rx_red_prio_0;
419 	u32	c_rx_red_prio_1;
420 	u32	c_rx_red_prio_2;
421 	u32	c_rx_red_prio_3;
422 	u32	c_rx_red_prio_4;
423 	u32	c_rx_red_prio_5;
424 	u32	c_rx_red_prio_6;
425 	u32	c_rx_red_prio_7;
426 	u32	c_rx_yellow_prio_0;
427 	u32	c_rx_yellow_prio_1;
428 	u32	c_rx_yellow_prio_2;
429 	u32	c_rx_yellow_prio_3;
430 	u32	c_rx_yellow_prio_4;
431 	u32	c_rx_yellow_prio_5;
432 	u32	c_rx_yellow_prio_6;
433 	u32	c_rx_yellow_prio_7;
434 	u32	c_rx_green_prio_0;
435 	u32	c_rx_green_prio_1;
436 	u32	c_rx_green_prio_2;
437 	u32	c_rx_green_prio_3;
438 	u32	c_rx_green_prio_4;
439 	u32	c_rx_green_prio_5;
440 	u32	c_rx_green_prio_6;
441 	u32	c_rx_green_prio_7;
442 	u32	reserved[20];
443 };
444 
445 struct vsc9953_tx_cntrs {
446 	u32	c_tx_oct;
447 	u32	c_tx_uc;
448 	u32	c_tx_mc;
449 	u32	c_tx_bc;
450 	u32	c_tx_col;
451 	u32	c_tx_drop;
452 	u32	c_tx_pause;
453 	u32	c_tx_sz_64;
454 	u32	c_tx_sz_65_127;
455 	u32	c_tx_sz_128_255;
456 	u32	c_tx_sz_256_511;
457 	u32	c_tx_sz_512_1023;
458 	u32	c_tx_sz_1024_1526;
459 	u32	c_tx_sz_jumbo;
460 	u32	c_tx_yellow_prio_0;
461 	u32	c_tx_yellow_prio_1;
462 	u32	c_tx_yellow_prio_2;
463 	u32	c_tx_yellow_prio_3;
464 	u32	c_tx_yellow_prio_4;
465 	u32	c_tx_yellow_prio_5;
466 	u32	c_tx_yellow_prio_6;
467 	u32	c_tx_yellow_prio_7;
468 	u32	c_tx_green_prio_0;
469 	u32	c_tx_green_prio_1;
470 	u32	c_tx_green_prio_2;
471 	u32	c_tx_green_prio_3;
472 	u32	c_tx_green_prio_4;
473 	u32	c_tx_green_prio_5;
474 	u32	c_tx_green_prio_6;
475 	u32	c_tx_green_prio_7;
476 	u32	c_tx_aged;
477 	u32	reserved[33];
478 };
479 
480 struct vsc9953_drop_cntrs {
481 	u32	c_dr_local;
482 	u32	c_dr_tail;
483 	u32	c_dr_yellow_prio_0;
484 	u32	c_dr_yellow_prio_1;
485 	u32	c_dr_yellow_prio_2;
486 	u32	c_dr_yellow_prio_3;
487 	u32	c_dr_yellow_prio_4;
488 	u32	c_dr_yellow_prio_5;
489 	u32	c_dr_yellow_prio_6;
490 	u32	c_dr_yellow_prio_7;
491 	u32	c_dr_green_prio_0;
492 	u32	c_dr_green_prio_1;
493 	u32	c_dr_green_prio_2;
494 	u32	c_dr_green_prio_3;
495 	u32	c_dr_green_prio_4;
496 	u32	c_dr_green_prio_5;
497 	u32	c_dr_green_prio_6;
498 	u32	c_dr_green_prio_7;
499 	u32	reserved[46];
500 };
501 
502 struct vsc9953_sys_stat {
503 	struct vsc9953_rx_cntrs	rx_cntrs;
504 	struct vsc9953_tx_cntrs	tx_cntrs;
505 	struct vsc9953_drop_cntrs	drop_cntrs;
506 	u32	reserved1[6];
507 };
508 
509 struct vsc9953_sys_sys {
510 	u32	reset_cfg;
511 	u32	reserved1;
512 	u32	vlan_etype_cfg;
513 	u32	port_mode[12];
514 	u32	front_port_mode[10];
515 	u32	frame_aging;
516 	u32	stat_cfg;
517 	u32	reserved2[50];
518 };
519 
520 struct vsc9953_sys_pause_cfg {
521 	u32	pause_cfg[11];
522 	u32	pause_tot_cfg;
523 	u32	tail_drop_level[11];
524 	u32	tot_tail_drop_lvl;
525 	u32	mac_fc_cfg[10];
526 };
527 
528 struct vsc9953_sys_mmgt {
529 	u16	free_cnt;
530 };
531 
532 struct vsc9953_system_reg {
533 	struct vsc9953_sys_stat	stat;
534 	struct vsc9953_sys_sys	sys;
535 	struct vsc9953_sys_pause_cfg	pause_cfg;
536 	struct vsc9953_sys_mmgt	mmgt;
537 };
538 
539 /* END VSC9953 SYS structure */
540 
541 /* VSC9953 REW structure */
542 
543 struct	vsc9953_rew_port {
544 	u32	port_vlan_cfg;
545 	u32	port_tag_cfg;
546 	u32	port_port_cfg;
547 	u32	port_dscp_cfg;
548 	u32	port_pcp_dei_qos_map_cfg[16];
549 	u32	reserved[12];
550 };
551 
552 struct	vsc9953_rew_common {
553 	u32	reserve[4];
554 	u32	dscp_remap_dp1_cfg[64];
555 	u32	dscp_remap_cfg[64];
556 };
557 
558 struct	vsc9953_rew_reg {
559 	struct vsc9953_rew_port	port[12];
560 	struct vsc9953_rew_common	common;
561 };
562 
563 /* END VSC9953 REW structure */
564 
565 /* VSC9953 DEVCPU_GCB structure */
566 
567 struct vsc9953_chip_regs {
568 	u32	chipd_id;
569 	u32	gpr;
570 	u32	soft_rst;
571 };
572 
573 struct vsc9953_gpio {
574 	u32	gpio_out_set[10];
575 	u32	gpio_out_clr[10];
576 	u32	gpio_out[10];
577 	u32	gpio_in[10];
578 };
579 
580 struct vsc9953_mii_mng {
581 	u32	miimstatus;
582 	u32	reserved1;
583 	u32	miimcmd;
584 	u32	miimdata;
585 	u32	miimcfg;
586 	u32	miimscan_0;
587 	u32	miimscan_1;
588 	u32	miiscan_lst_rslts;
589 	u32	miiscan_lst_rslts_valid;
590 };
591 
592 struct vsc9953_mii_read_scan {
593 	u32	mii_scan_results_sticky[2];
594 };
595 
596 struct vsc9953_devcpu_gcb {
597 	struct vsc9953_chip_regs	chip_regs;
598 	struct vsc9953_gpio		gpio;
599 	struct vsc9953_mii_mng	mii_mng[2];
600 	struct vsc9953_mii_read_scan	mii_read_scan;
601 };
602 
603 /* END VSC9953 DEVCPU_GCB structure */
604 
605 /* VSC9953 IS* structure */
606 
607 struct vsc9953_vcap_core_cfg {
608 	u32	vcap_update_ctrl;
609 	u32	vcap_mv_cfg;
610 };
611 
612 struct vsc9953_vcap {
613 	struct vsc9953_vcap_core_cfg	vcap_core_cfg;
614 };
615 
616 /* END VSC9953 IS* structure */
617 
618 #define VSC9953_PORT_INFO_INITIALIZER(idx) \
619 {									\
620 	.enabled	= 0,						\
621 	.phyaddr	= 0,						\
622 	.index		= idx,						\
623 	.phy_regs	= NULL,						\
624 	.enet_if	= PHY_INTERFACE_MODE_NONE,			\
625 	.bus		= NULL,						\
626 	.phydev		= NULL,						\
627 }
628 
629 /* Structure to describe a VSC9953 port */
630 struct vsc9953_port_info {
631 	u8	enabled;
632 	u8	phyaddr;
633 	int	index;
634 	void	*phy_regs;
635 	phy_interface_t	enet_if;
636 	struct mii_dev	*bus;
637 	struct phy_device	*phydev;
638 };
639 
640 /* Structure to describe a VSC9953 switch */
641 struct vsc9953_info {
642 	struct vsc9953_port_info	port[VSC9953_MAX_PORTS];
643 };
644 
645 void vsc9953_init(bd_t *bis);
646 
647 void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
648 void vsc9953_port_info_set_phy_address(int port_no, int address);
649 void vsc9953_port_enable(int port_no);
650 void vsc9953_port_disable(int port_no);
651 void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
652 
653 #endif /* _VSC9953_H_ */
654