1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2013, 2015 Freescale Semiconductor, Inc. 4 * 5 * Driver for the Vitesse VSC9953 L2 Switch 6 */ 7 8 #ifndef _VSC9953_H_ 9 #define _VSC9953_H_ 10 11 #include <config.h> 12 #include <miiphy.h> 13 #include <asm/types.h> 14 15 #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000) 16 17 #define VSC9953_SYS_OFFSET 0x010000 18 #define VSC9953_REW_OFFSET 0x030000 19 #define VSC9953_DEV_GMII_OFFSET 0x100000 20 #define VSC9953_QSYS_OFFSET 0x200000 21 #define VSC9953_ANA_OFFSET 0x280000 22 #define VSC9953_DEVCPU_GCB 0x070000 23 #define VSC9953_ES0 0x040000 24 #define VSC9953_IS1 0x050000 25 #define VSC9953_IS2 0x060000 26 27 #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000 28 #define VSC9953_PHY_REGS_OFFST 0x0000AC 29 30 /* Macros for vsc9953_chip_regs.soft_rst register */ 31 #define VSC9953_SOFT_SWC_RST_ENA 0x00000001 32 33 /* Macros for vsc9953_sys_sys.reset_cfg register */ 34 #define VSC9953_CORE_ENABLE 0x80 35 #define VSC9953_MEM_ENABLE 0x40 36 #define VSC9953_MEM_INIT 0x20 37 38 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */ 39 #define VSC9953_MAC_ENA_CFG 0x00000011 40 41 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */ 42 #define VSC9953_MAC_MODE_CFG 0x00000011 43 44 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */ 45 #define VSC9953_MAC_IFG_CFG 0x00000515 46 47 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */ 48 #define VSC9953_MAC_HDX_CFG 0x00001043 49 50 /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */ 51 #define VSC9953_MAC_MAX_LEN 0x000005ee 52 53 /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */ 54 #define VSC9953_CLOCK_CFG 0x00000001 55 #define VSC9953_CLOCK_CFG_1000M 0x00000001 56 57 /* Macros for vsc9953_sys_sys.front_port_mode register */ 58 #define VSC9953_FRONT_PORT_MODE 0x00000000 59 60 /* Macros for vsc9953_ana_pfc.pfc_cfg register */ 61 #define VSC9953_PFC_FC 0x00000001 62 #define VSC9953_PFC_FC_QSGMII 0x00000000 63 64 /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */ 65 #define VSC9953_MAC_FC_CFG 0x04700000 66 #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000 67 68 /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */ 69 #define VSC9953_PAUSE_CFG 0x001ffffe 70 71 /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */ 72 #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff 73 74 /* Macros for vsc9953_sys_sys.stat_cfg register */ 75 #define VSC9953_STAT_CLEAR_RX 0x00000400 76 #define VSC9953_STAT_CLEAR_TX 0x00000800 77 #define VSC9953_STAT_CLEAR_DR 0x00001000 78 79 /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */ 80 #define VSC9953_VCAP_MV_CFG 0x0000ffff 81 #define VSC9953_VCAP_UPDATE_CTRL 0x01000004 82 83 /* Macros for register vsc9953_ana_ana_tables.mac_access register */ 84 #define VSC9953_MAC_CMD_IDLE 0x00000000 85 #define VSC9953_MAC_CMD_LEARN 0x00000001 86 #define VSC9953_MAC_CMD_FORGET 0x00000002 87 #define VSC9953_MAC_CMD_AGE 0x00000003 88 #define VSC9953_MAC_CMD_NEXT 0x00000004 89 #define VSC9953_MAC_CMD_READ 0x00000006 90 #define VSC9953_MAC_CMD_WRITE 0x00000007 91 #define VSC9953_MAC_CMD_MASK 0x00000007 92 #define VSC9953_MAC_CMD_VALID 0x00000800 93 #define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000 94 #define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200 95 #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400 96 #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600 97 #define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600 98 #define VSC9953_MAC_DESTIDX_MASK 0x000001f8 99 #define VSC9953_MAC_VID_MASK 0x1fff0000 100 #define VSC9953_MAC_MACH_MASK 0x0000ffff 101 102 /* Macros for vsc9953_ana_port.vlan_cfg register */ 103 #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000 104 #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000 105 #define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000 106 #define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000 107 #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff 108 109 /* Macros for vsc9953_rew_port.port_vlan_cfg register */ 110 #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff 111 112 /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */ 113 #define VSC9953_ANA_TBL_VID_MASK 0x00000fff 114 115 /* Macros for vsc9953_ana_ana_tables.vlan_access register */ 116 #define VSC9953_VLAN_PORT_MASK 0x00001ffc 117 #define VSC9953_VLAN_CMD_MASK 0x00000003 118 #define VSC9953_VLAN_CMD_IDLE 0x00000000 119 #define VSC9953_VLAN_CMD_READ 0x00000001 120 #define VSC9953_VLAN_CMD_WRITE 0x00000002 121 #define VSC9953_VLAN_CMD_INIT 0x00000003 122 123 /* Macros for vsc9953_ana_port.port_cfg register */ 124 #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080 125 #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100 126 #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200 127 #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400 128 #define VSC9953_PORT_CFG_PORTID_MASK 0x0000003c 129 130 /* Macros for vsc9953_qsys_sys.switch_port_mode register */ 131 #define VSC9953_PORT_ENA 0x00002000 132 133 /* Macros for vsc9953_ana_ana.agen_ctrl register */ 134 #define VSC9953_FID_MASK_ALL 0x00fff000 135 136 /* Macros for vsc9953_ana_ana.adv_learn register */ 137 #define VSC9953_VLAN_CHK 0x00000400 138 139 /* Macros for vsc9953_ana_ana.auto_age register */ 140 #define VSC9953_AUTOAGE_PERIOD_MASK 0x001ffffe 141 142 /* Macros for vsc9953_rew_port.port_tag_cfg register */ 143 #define VSC9953_TAG_CFG_MASK 0x00000180 144 #define VSC9953_TAG_CFG_NONE 0x00000000 145 #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080 146 #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100 147 #define VSC9953_TAG_CFG_ALL 0x00000180 148 #define VSC9953_TAG_VID_PVID 0x00000010 149 150 /* Macros for vsc9953_ana_ana.anag_efil register */ 151 #define VSC9953_AGE_PORT_EN 0x00080000 152 #define VSC9953_AGE_PORT_MASK 0x0007c000 153 #define VSC9953_AGE_VID_EN 0x00002000 154 #define VSC9953_AGE_VID_MASK 0x00001fff 155 156 /* Macros for vsc9953_ana_ana_tables.mach_data register */ 157 #define VSC9953_MACHDATA_VID_MASK 0x1fff0000 158 159 /* Macros for vsc9953_ana_common.aggr_cfg register */ 160 #define VSC9953_AC_RND_ENA 0x00000080 161 #define VSC9953_AC_DMAC_ENA 0x00000040 162 #define VSC9953_AC_SMAC_ENA 0x00000020 163 #define VSC9953_AC_IP6_LBL_ENA 0x00000010 164 #define VSC9953_AC_IP6_TCPUDP_ENA 0x00000008 165 #define VSC9953_AC_IP4_SIPDIP_ENA 0x00000004 166 #define VSC9953_AC_IP4_TCPUDP_ENA 0x00000002 167 #define VSC9953_AC_MASK 0x000000fe 168 169 /* Macros for vsc9953_ana_pgid.port_grp_id[] registers */ 170 #define VSC9953_PGID_PORT_MASK 0x000003ff 171 172 #define VSC9953_MAX_PORTS 10 173 #define VSC9953_PORT_CHECK(port) \ 174 (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1) 175 #define VSC9953_INTERNAL_PORT_CHECK(port) ( \ 176 ( \ 177 (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \ 178 ) ? 0 : 1 \ 179 ) 180 #define VSC9953_MAX_VLAN 4096 181 #define VSC9953_VLAN_CHECK(vid) \ 182 (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1) 183 #define VSC9953_DEFAULT_AGE_TIME 300 184 185 #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0" 186 187 #define MIIMIND_OPR_PEND 0x00000004 188 189 struct vsc9953_mdio_info { 190 struct vsc9953_mii_mng *regs; 191 char *name; 192 }; 193 194 /* VSC9953 ANA structure */ 195 196 struct vsc9953_ana_port { 197 u32 vlan_cfg; 198 u32 drop_cfg; 199 u32 qos_cfg; 200 u32 vcap_cfg; 201 u32 vcap_s1_key_cfg[3]; 202 u32 vcap_s2_cfg; 203 u32 qos_pcp_dei_map_cfg[16]; 204 u32 cpu_fwd_cfg; 205 u32 cpu_fwd_bpdu_cfg; 206 u32 cpu_fwd_garp_cfg; 207 u32 cpu_fwd_ccm_cfg; 208 u32 port_cfg; 209 u32 pol_cfg; 210 u32 reserved[34]; 211 }; 212 213 struct vsc9953_ana_pol { 214 u32 pol_pir_cfg; 215 u32 pol_cir_cfg; 216 u32 pol_mode_cfg; 217 u32 pol_pir_state; 218 u32 pol_cir_state; 219 u32 reserved1[3]; 220 }; 221 222 struct vsc9953_ana_ana_tables { 223 u32 entry_lim[11]; 224 u32 an_moved; 225 u32 mach_data; 226 u32 macl_data; 227 u32 mac_access; 228 u32 mact_indx; 229 u32 vlan_access; 230 u32 vlan_tidx; 231 }; 232 233 struct vsc9953_ana_ana { 234 u32 adv_learn; 235 u32 vlan_mask; 236 u32 reserved; 237 u32 anag_efil; 238 u32 an_events; 239 u32 storm_limit_burst; 240 u32 storm_limit_cfg[4]; 241 u32 isolated_prts; 242 u32 community_ports; 243 u32 auto_age; 244 u32 mac_options; 245 u32 learn_disc; 246 u32 agen_ctrl; 247 u32 mirror_ports; 248 u32 emirror_ports; 249 u32 flooding; 250 u32 flooding_ipmc; 251 u32 sflow_cfg[11]; 252 u32 port_mode[12]; 253 }; 254 255 #define PGID_DST_START 0 256 #define PGID_AGGR_START 64 257 #define PGID_SRC_START 80 258 259 struct vsc9953_ana_pgid { 260 u32 port_grp_id[91]; 261 }; 262 263 struct vsc9953_ana_pfc { 264 u32 pfc_cfg; 265 u32 reserved1[15]; 266 }; 267 268 struct vsc9953_ana_pol_misc { 269 u32 pol_flowc[10]; 270 u32 reserved1[17]; 271 u32 pol_hyst; 272 }; 273 274 struct vsc9953_ana_common { 275 u32 aggr_cfg; 276 u32 cpuq_cfg; 277 u32 cpuq_8021_cfg; 278 u32 dscp_cfg; 279 u32 dscp_rewr_cfg; 280 u32 vcap_rng_type_cfg; 281 u32 vcap_rng_val_cfg; 282 u32 discard_cfg; 283 u32 fid_cfg; 284 }; 285 286 struct vsc9953_analyzer { 287 struct vsc9953_ana_port port[11]; 288 u32 reserved1[9536]; 289 struct vsc9953_ana_pol pol[164]; 290 struct vsc9953_ana_ana_tables ana_tables; 291 u32 reserved2[14]; 292 struct vsc9953_ana_ana ana; 293 u32 reserved3[21]; 294 struct vsc9953_ana_pgid port_id_tbl; 295 u32 reserved4[549]; 296 struct vsc9953_ana_pfc pfc[10]; 297 struct vsc9953_ana_pol_misc pol_misc; 298 u32 reserved5[196]; 299 struct vsc9953_ana_common common; 300 }; 301 /* END VSC9953 ANA structure t*/ 302 303 /* VSC9953 DEV_GMII structure */ 304 305 struct vsc9953_dev_gmii_port_mode { 306 u32 clock_cfg; 307 u32 port_misc; 308 u32 reserved1; 309 u32 eee_cfg; 310 }; 311 312 struct vsc9953_dev_gmii_mac_cfg_status { 313 u32 mac_ena_cfg; 314 u32 mac_mode_cfg; 315 u32 mac_maxlen_cfg; 316 u32 mac_tags_cfg; 317 u32 mac_adv_chk_cfg; 318 u32 mac_ifg_cfg; 319 u32 mac_hdx_cfg; 320 u32 mac_fc_mac_low_cfg; 321 u32 mac_fc_mac_high_cfg; 322 u32 mac_sticky; 323 }; 324 325 struct vsc9953_dev_gmii { 326 struct vsc9953_dev_gmii_port_mode port_mode; 327 struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status; 328 }; 329 330 /* END VSC9953 DEV_GMII structure */ 331 332 /* VSC9953 QSYS structure */ 333 334 struct vsc9953_qsys_hsch { 335 u32 cir_cfg; 336 u32 reserved1; 337 u32 se_cfg; 338 u32 se_dwrr_cfg[8]; 339 u32 cir_state; 340 u32 reserved2[20]; 341 }; 342 343 struct vsc9953_qsys_sys { 344 u32 port_mode[12]; 345 u32 switch_port_mode[11]; 346 u32 stat_cnt_cfg; 347 u32 eee_cfg[10]; 348 u32 eee_thrs; 349 u32 igr_no_sharing; 350 u32 egr_no_sharing; 351 u32 sw_status[11]; 352 u32 ext_cpu_cfg; 353 u32 cpu_group_map; 354 u32 reserved1[23]; 355 }; 356 357 struct vsc9953_qsys_qos_cfg { 358 u32 red_profile[16]; 359 u32 res_qos_mode; 360 }; 361 362 struct vsc9953_qsys_drop_cfg { 363 u32 egr_drop_mode; 364 }; 365 366 struct vsc9953_qsys_mmgt { 367 u32 eq_cntrl; 368 u32 reserved1; 369 }; 370 371 struct vsc9953_qsys_hsch_misc { 372 u32 hsch_misc_cfg; 373 u32 reserved1[546]; 374 }; 375 376 struct vsc9953_qsys_res_ctrl { 377 u32 res_cfg; 378 u32 res_stat; 379 380 }; 381 382 struct vsc9953_qsys_reg { 383 struct vsc9953_qsys_hsch hsch[108]; 384 struct vsc9953_qsys_sys sys; 385 struct vsc9953_qsys_qos_cfg qos_cfg; 386 struct vsc9953_qsys_drop_cfg drop_cfg; 387 struct vsc9953_qsys_mmgt mmgt; 388 struct vsc9953_qsys_hsch_misc hsch_misc; 389 struct vsc9953_qsys_res_ctrl res_ctrl[1024]; 390 }; 391 392 /* END VSC9953 QSYS structure */ 393 394 /* VSC9953 SYS structure */ 395 396 struct vsc9953_rx_cntrs { 397 u32 c_rx_oct; 398 u32 c_rx_uc; 399 u32 c_rx_mc; 400 u32 c_rx_bc; 401 u32 c_rx_short; 402 u32 c_rx_frag; 403 u32 c_rx_jabber; 404 u32 c_rx_crc; 405 u32 c_rx_symbol_err; 406 u32 c_rx_sz_64; 407 u32 c_rx_sz_65_127; 408 u32 c_rx_sz_128_255; 409 u32 c_rx_sz_256_511; 410 u32 c_rx_sz_512_1023; 411 u32 c_rx_sz_1024_1526; 412 u32 c_rx_sz_jumbo; 413 u32 c_rx_pause; 414 u32 c_rx_control; 415 u32 c_rx_long; 416 u32 c_rx_cat_drop; 417 u32 c_rx_red_prio_0; 418 u32 c_rx_red_prio_1; 419 u32 c_rx_red_prio_2; 420 u32 c_rx_red_prio_3; 421 u32 c_rx_red_prio_4; 422 u32 c_rx_red_prio_5; 423 u32 c_rx_red_prio_6; 424 u32 c_rx_red_prio_7; 425 u32 c_rx_yellow_prio_0; 426 u32 c_rx_yellow_prio_1; 427 u32 c_rx_yellow_prio_2; 428 u32 c_rx_yellow_prio_3; 429 u32 c_rx_yellow_prio_4; 430 u32 c_rx_yellow_prio_5; 431 u32 c_rx_yellow_prio_6; 432 u32 c_rx_yellow_prio_7; 433 u32 c_rx_green_prio_0; 434 u32 c_rx_green_prio_1; 435 u32 c_rx_green_prio_2; 436 u32 c_rx_green_prio_3; 437 u32 c_rx_green_prio_4; 438 u32 c_rx_green_prio_5; 439 u32 c_rx_green_prio_6; 440 u32 c_rx_green_prio_7; 441 u32 reserved[20]; 442 }; 443 444 struct vsc9953_tx_cntrs { 445 u32 c_tx_oct; 446 u32 c_tx_uc; 447 u32 c_tx_mc; 448 u32 c_tx_bc; 449 u32 c_tx_col; 450 u32 c_tx_drop; 451 u32 c_tx_pause; 452 u32 c_tx_sz_64; 453 u32 c_tx_sz_65_127; 454 u32 c_tx_sz_128_255; 455 u32 c_tx_sz_256_511; 456 u32 c_tx_sz_512_1023; 457 u32 c_tx_sz_1024_1526; 458 u32 c_tx_sz_jumbo; 459 u32 c_tx_yellow_prio_0; 460 u32 c_tx_yellow_prio_1; 461 u32 c_tx_yellow_prio_2; 462 u32 c_tx_yellow_prio_3; 463 u32 c_tx_yellow_prio_4; 464 u32 c_tx_yellow_prio_5; 465 u32 c_tx_yellow_prio_6; 466 u32 c_tx_yellow_prio_7; 467 u32 c_tx_green_prio_0; 468 u32 c_tx_green_prio_1; 469 u32 c_tx_green_prio_2; 470 u32 c_tx_green_prio_3; 471 u32 c_tx_green_prio_4; 472 u32 c_tx_green_prio_5; 473 u32 c_tx_green_prio_6; 474 u32 c_tx_green_prio_7; 475 u32 c_tx_aged; 476 u32 reserved[33]; 477 }; 478 479 struct vsc9953_drop_cntrs { 480 u32 c_dr_local; 481 u32 c_dr_tail; 482 u32 c_dr_yellow_prio_0; 483 u32 c_dr_yellow_prio_1; 484 u32 c_dr_yellow_prio_2; 485 u32 c_dr_yellow_prio_3; 486 u32 c_dr_yellow_prio_4; 487 u32 c_dr_yellow_prio_5; 488 u32 c_dr_yellow_prio_6; 489 u32 c_dr_yellow_prio_7; 490 u32 c_dr_green_prio_0; 491 u32 c_dr_green_prio_1; 492 u32 c_dr_green_prio_2; 493 u32 c_dr_green_prio_3; 494 u32 c_dr_green_prio_4; 495 u32 c_dr_green_prio_5; 496 u32 c_dr_green_prio_6; 497 u32 c_dr_green_prio_7; 498 u32 reserved[46]; 499 }; 500 501 struct vsc9953_sys_stat { 502 struct vsc9953_rx_cntrs rx_cntrs; 503 struct vsc9953_tx_cntrs tx_cntrs; 504 struct vsc9953_drop_cntrs drop_cntrs; 505 u32 reserved1[6]; 506 }; 507 508 struct vsc9953_sys_sys { 509 u32 reset_cfg; 510 u32 reserved1; 511 u32 vlan_etype_cfg; 512 u32 port_mode[12]; 513 u32 front_port_mode[10]; 514 u32 frame_aging; 515 u32 stat_cfg; 516 u32 reserved2[50]; 517 }; 518 519 struct vsc9953_sys_pause_cfg { 520 u32 pause_cfg[11]; 521 u32 pause_tot_cfg; 522 u32 tail_drop_level[11]; 523 u32 tot_tail_drop_lvl; 524 u32 mac_fc_cfg[10]; 525 }; 526 527 struct vsc9953_sys_mmgt { 528 u16 free_cnt; 529 }; 530 531 struct vsc9953_system_reg { 532 struct vsc9953_sys_stat stat; 533 struct vsc9953_sys_sys sys; 534 struct vsc9953_sys_pause_cfg pause_cfg; 535 struct vsc9953_sys_mmgt mmgt; 536 }; 537 538 /* END VSC9953 SYS structure */ 539 540 /* VSC9953 REW structure */ 541 542 struct vsc9953_rew_port { 543 u32 port_vlan_cfg; 544 u32 port_tag_cfg; 545 u32 port_port_cfg; 546 u32 port_dscp_cfg; 547 u32 port_pcp_dei_qos_map_cfg[16]; 548 u32 reserved[12]; 549 }; 550 551 struct vsc9953_rew_common { 552 u32 reserve[4]; 553 u32 dscp_remap_dp1_cfg[64]; 554 u32 dscp_remap_cfg[64]; 555 }; 556 557 struct vsc9953_rew_reg { 558 struct vsc9953_rew_port port[12]; 559 struct vsc9953_rew_common common; 560 }; 561 562 /* END VSC9953 REW structure */ 563 564 /* VSC9953 DEVCPU_GCB structure */ 565 566 struct vsc9953_chip_regs { 567 u32 chipd_id; 568 u32 gpr; 569 u32 soft_rst; 570 }; 571 572 struct vsc9953_gpio { 573 u32 gpio_out_set[10]; 574 u32 gpio_out_clr[10]; 575 u32 gpio_out[10]; 576 u32 gpio_in[10]; 577 }; 578 579 struct vsc9953_mii_mng { 580 u32 miimstatus; 581 u32 reserved1; 582 u32 miimcmd; 583 u32 miimdata; 584 u32 miimcfg; 585 u32 miimscan_0; 586 u32 miimscan_1; 587 u32 miiscan_lst_rslts; 588 u32 miiscan_lst_rslts_valid; 589 }; 590 591 struct vsc9953_mii_read_scan { 592 u32 mii_scan_results_sticky[2]; 593 }; 594 595 struct vsc9953_devcpu_gcb { 596 struct vsc9953_chip_regs chip_regs; 597 struct vsc9953_gpio gpio; 598 struct vsc9953_mii_mng mii_mng[2]; 599 struct vsc9953_mii_read_scan mii_read_scan; 600 }; 601 602 /* END VSC9953 DEVCPU_GCB structure */ 603 604 /* VSC9953 IS* structure */ 605 606 struct vsc9953_vcap_core_cfg { 607 u32 vcap_update_ctrl; 608 u32 vcap_mv_cfg; 609 }; 610 611 struct vsc9953_vcap { 612 struct vsc9953_vcap_core_cfg vcap_core_cfg; 613 }; 614 615 /* END VSC9953 IS* structure */ 616 617 #define VSC9953_PORT_INFO_INITIALIZER(idx) \ 618 { \ 619 .enabled = 0, \ 620 .phyaddr = 0, \ 621 .index = idx, \ 622 .phy_regs = NULL, \ 623 .enet_if = PHY_INTERFACE_MODE_NONE, \ 624 .bus = NULL, \ 625 .phydev = NULL, \ 626 } 627 628 /* Structure to describe a VSC9953 port */ 629 struct vsc9953_port_info { 630 u8 enabled; 631 u8 phyaddr; 632 int index; 633 void *phy_regs; 634 phy_interface_t enet_if; 635 struct mii_dev *bus; 636 struct phy_device *phydev; 637 }; 638 639 /* Structure to describe a VSC9953 switch */ 640 struct vsc9953_info { 641 struct vsc9953_port_info port[VSC9953_MAX_PORTS]; 642 }; 643 644 void vsc9953_init(bd_t *bis); 645 646 void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus); 647 void vsc9953_port_info_set_phy_address(int port_no, int address); 648 void vsc9953_port_enable(int port_no); 649 void vsc9953_port_disable(int port_no); 650 void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int); 651 652 #endif /* _VSC9953_H_ */ 653