1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2002 4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 5 * Keith Outwater, keith_outwater@mvis.com 6 */ 7 8 #ifndef _VIRTEX2_H_ 9 #define _VIRTEX2_H_ 10 11 #include <xilinx.h> 12 13 /* 14 * Slave SelectMap Implementation function table. 15 */ 16 typedef struct { 17 xilinx_pre_fn pre; 18 xilinx_pgm_fn pgm; 19 xilinx_init_fn init; 20 xilinx_err_fn err; 21 xilinx_done_fn done; 22 xilinx_clk_fn clk; 23 xilinx_cs_fn cs; 24 xilinx_wr_fn wr; 25 xilinx_rdata_fn rdata; 26 xilinx_wdata_fn wdata; 27 xilinx_busy_fn busy; 28 xilinx_abort_fn abort; 29 xilinx_post_fn post; 30 } xilinx_virtex2_slave_selectmap_fns; 31 32 /* Slave Serial Implementation function table */ 33 typedef struct { 34 xilinx_pgm_fn pgm; 35 xilinx_clk_fn clk; 36 xilinx_rdata_fn rdata; 37 xilinx_wdata_fn wdata; 38 } xilinx_virtex2_slave_serial_fns; 39 40 #if defined(CONFIG_FPGA_VIRTEX2) 41 extern struct xilinx_fpga_op virtex2_op; 42 # define FPGA_VIRTEX2_OPS &virtex2_op 43 #else 44 # define FPGA_VIRTEX2_OPS NULL 45 #endif 46 47 /* Device Image Sizes (in bytes) 48 *********************************************************************/ 49 #define XILINX_XC2V40_SIZE (338208 / 8) 50 #define XILINX_XC2V80_SIZE (597408 / 8) 51 #define XILINX_XC2V250_SIZE (1591584 / 8) 52 #define XILINX_XC2V500_SIZE (2557857 / 8) 53 #define XILINX_XC2V1000_SIZE (3749408 / 8) 54 #define XILINX_XC2V1500_SIZE (5166240 / 8) 55 #define XILINX_XC2V2000_SIZE (6808352 / 8) 56 #define XILINX_XC2V3000_SIZE (9589408 / 8) 57 #define XILINX_XC2V4000_SIZE (14220192 / 8) 58 #define XILINX_XC2V6000_SIZE (19752096 / 8) 59 #define XILINX_XC2V8000_SIZE (26185120 / 8) 60 #define XILINX_XC2V10000_SIZE (33519264 / 8) 61 62 /* Descriptor Macros 63 *********************************************************************/ 64 #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ 65 { xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \ 66 FPGA_VIRTEX2_OPS } 67 68 #define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ 69 { xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \ 70 FPGA_VIRTEX2_OPS } 71 72 #define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ 73 { xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \ 74 FPGA_VIRTEX2_OPS } 75 76 #define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ 77 { xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \ 78 FPGA_VIRTEX2_OPS } 79 80 #define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ 81 { xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \ 82 FPGA_VIRTEX2_OPS } 83 84 #define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ 85 { xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \ 86 FPGA_VIRTEX2_OPS } 87 88 #define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ 89 { xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \ 90 FPGA_VIRTEX2_OPS } 91 92 #define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ 93 { xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \ 94 FPGA_VIRTEX2_OPS } 95 96 #define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ 97 { xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \ 98 FPGA_VIRTEX2_OPS } 99 100 #define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ 101 { xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \ 102 FPGA_VIRTEX2_OPS } 103 104 #define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ 105 { xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \ 106 FPGA_VIRTEX2_OPS } 107 108 #define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ 109 { xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \ 110 FPGA_VIRTEX2_OPS } 111 112 #endif /* _VIRTEX2_H_ */ 113