xref: /openbmc/u-boot/include/usb/fusbh200.h (revision e82a316d)
1*e82a316dSKuo-Jung Su /*
2*e82a316dSKuo-Jung Su  * Faraday USB 2.0 EHCI Controller
3*e82a316dSKuo-Jung Su  *
4*e82a316dSKuo-Jung Su  * (C) Copyright 2010 Faraday Technology
5*e82a316dSKuo-Jung Su  * Dante Su <dantesu@faraday-tech.com>
6*e82a316dSKuo-Jung Su  *
7*e82a316dSKuo-Jung Su  * This file is released under the terms of GPL v2 and any later version.
8*e82a316dSKuo-Jung Su  * See the file COPYING in the root directory of the source tree for details.
9*e82a316dSKuo-Jung Su  */
10*e82a316dSKuo-Jung Su 
11*e82a316dSKuo-Jung Su #ifndef _FUSBH200_H
12*e82a316dSKuo-Jung Su #define _FUSBH200_H
13*e82a316dSKuo-Jung Su 
14*e82a316dSKuo-Jung Su struct fusbh200_regs {
15*e82a316dSKuo-Jung Su 	struct {
16*e82a316dSKuo-Jung Su 		uint32_t data[4];
17*e82a316dSKuo-Jung Su 	} hccr;			/* 0x00 - 0x0f: hccr */
18*e82a316dSKuo-Jung Su 	struct {
19*e82a316dSKuo-Jung Su 		uint32_t data[9];
20*e82a316dSKuo-Jung Su 	} hcor;			/* 0x10 - 0x33: hcor */
21*e82a316dSKuo-Jung Su 	uint32_t easstr;/* 0x34: EOF&Async. Sched. Sleep Timer Register */
22*e82a316dSKuo-Jung Su 	uint32_t rsvd[2];
23*e82a316dSKuo-Jung Su 	uint32_t bmcsr;	/* 0x40: Bus Monitor Control Status Register */
24*e82a316dSKuo-Jung Su 	uint32_t bmisr;	/* 0x44: Bus Monitor Interrupt Status Register */
25*e82a316dSKuo-Jung Su 	uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */
26*e82a316dSKuo-Jung Su };
27*e82a316dSKuo-Jung Su 
28*e82a316dSKuo-Jung Su /* EOF & Async. Schedule Sleep Timer Register */
29*e82a316dSKuo-Jung Su #define EASSTR_RUNNING  (1 << 6) /* Put transceiver in running/resume mode */
30*e82a316dSKuo-Jung Su #define EASSTR_SUSPEND  (0 << 6) /* Put transceiver in suspend mode */
31*e82a316dSKuo-Jung Su #define EASSTR_EOF2(x)  (((x) & 0x3) << 4) /* EOF 2 Timing */
32*e82a316dSKuo-Jung Su #define EASSTR_EOF1(x)  (((x) & 0x3) << 2) /* EOF 1 Timing */
33*e82a316dSKuo-Jung Su #define EASSTR_ASST(x)  (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */
34*e82a316dSKuo-Jung Su 
35*e82a316dSKuo-Jung Su /* Bus Monitor Control Status Register */
36*e82a316dSKuo-Jung Su #define BMCSR_SPD_HIGH  (2 << 9) /* Speed of the attached device */
37*e82a316dSKuo-Jung Su #define BMCSR_SPD_LOW   (1 << 9)
38*e82a316dSKuo-Jung Su #define BMCSR_SPD_FULL  (0 << 9)
39*e82a316dSKuo-Jung Su #define BMCSR_SPD_MASK  (3 << 9)
40*e82a316dSKuo-Jung Su #define BMCSR_SPD_SHIFT 9
41*e82a316dSKuo-Jung Su #define BMCSR_SPD(x)    ((x >> 9) & 0x03)
42*e82a316dSKuo-Jung Su #define BMCSR_VBUS      (1 << 8) /* VBUS Valid */
43*e82a316dSKuo-Jung Su #define BMCSR_VBUS_OFF  (1 << 4) /* VBUS Off */
44*e82a316dSKuo-Jung Su #define BMCSR_VBUS_ON   (0 << 4) /* VBUS On */
45*e82a316dSKuo-Jung Su #define BMCSR_IRQLH     (1 << 3) /* IRQ triggered at level-high */
46*e82a316dSKuo-Jung Su #define BMCSR_IRQLL     (0 << 3) /* IRQ triggered at level-low */
47*e82a316dSKuo-Jung Su #define BMCSR_HALFSPD   (1 << 2) /* Half speed mode for FPGA test */
48*e82a316dSKuo-Jung Su #define BMCSR_HFT_LONG  (1 << 1) /* HDISCON noise filter = 270 us*/
49*e82a316dSKuo-Jung Su #define BMCSR_HFT       (0 << 1) /* HDISCON noise filter = 135 us*/
50*e82a316dSKuo-Jung Su #define BMCSR_VFT_LONG  (1 << 1) /* VBUS noise filter = 472 us*/
51*e82a316dSKuo-Jung Su #define BMCSR_VFT       (0 << 1) /* VBUS noise filter = 135 us*/
52*e82a316dSKuo-Jung Su 
53*e82a316dSKuo-Jung Su /* Bus Monitor Interrupt Status Register */
54*e82a316dSKuo-Jung Su /* Bus Monitor Interrupt Enable Register */
55*e82a316dSKuo-Jung Su #define BMISR_DMAERR    (1 << 4) /* DMA error */
56*e82a316dSKuo-Jung Su #define BMISR_DMA       (1 << 3) /* DMA complete */
57*e82a316dSKuo-Jung Su #define BMISR_DEVRM     (1 << 2) /* device removed */
58*e82a316dSKuo-Jung Su #define BMISR_OVD       (1 << 1) /* over-current detected */
59*e82a316dSKuo-Jung Su #define BMISR_VBUSERR   (1 << 0) /* VBUS error */
60*e82a316dSKuo-Jung Su 
61*e82a316dSKuo-Jung Su #endif
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