1 /* 2 * (C) Copyright 2009 3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef __DW_UDC_H 9 #define __DW_UDC_H 10 11 /* 12 * Defines for USBD 13 * 14 * The udc_ahb controller has three AHB slaves: 15 * 16 * 1. THe UDC registers 17 * 2. The plug detect 18 * 3. The RX/TX FIFO 19 */ 20 21 #define MAX_ENDPOINTS 16 22 23 struct udc_endp_regs { 24 u32 endp_cntl; 25 u32 endp_status; 26 u32 endp_bsorfn; 27 u32 endp_maxpacksize; 28 u32 reserved_1; 29 u32 endp_desc_point; 30 u32 reserved_2; 31 u32 write_done; 32 }; 33 34 /* Endpoint Control Register definitions */ 35 36 #define ENDP_CNTL_STALL 0x00000001 37 #define ENDP_CNTL_FLUSH 0x00000002 38 #define ENDP_CNTL_SNOOP 0x00000004 39 #define ENDP_CNTL_POLL 0x00000008 40 #define ENDP_CNTL_CONTROL 0x00000000 41 #define ENDP_CNTL_ISO 0x00000010 42 #define ENDP_CNTL_BULK 0x00000020 43 #define ENDP_CNTL_INT 0x00000030 44 #define ENDP_CNTL_NAK 0x00000040 45 #define ENDP_CNTL_SNAK 0x00000080 46 #define ENDP_CNTL_CNAK 0x00000100 47 #define ENDP_CNTL_RRDY 0x00000200 48 49 /* Endpoint Satus Register definitions */ 50 51 #define ENDP_STATUS_PIDMSK 0x0000000f 52 #define ENDP_STATUS_OUTMSK 0x00000030 53 #define ENDP_STATUS_OUT_NONE 0x00000000 54 #define ENDP_STATUS_OUT_DATA 0x00000010 55 #define ENDP_STATUS_OUT_SETUP 0x00000020 56 #define ENDP_STATUS_IN 0x00000040 57 #define ENDP_STATUS_BUFFNAV 0x00000080 58 #define ENDP_STATUS_FATERR 0x00000100 59 #define ENDP_STATUS_HOSTBUSERR 0x00000200 60 #define ENDP_STATUS_TDC 0x00000400 61 #define ENDP_STATUS_RXPKTMSK 0x003ff800 62 63 struct udc_regs { 64 struct udc_endp_regs in_regs[MAX_ENDPOINTS]; 65 struct udc_endp_regs out_regs[MAX_ENDPOINTS]; 66 u32 dev_conf; 67 u32 dev_cntl; 68 u32 dev_stat; 69 u32 dev_int; 70 u32 dev_int_mask; 71 u32 endp_int; 72 u32 endp_int_mask; 73 u32 reserved_3[0x39]; 74 u32 reserved_4; /* offset 0x500 */ 75 u32 udc_endp_reg[MAX_ENDPOINTS]; 76 }; 77 78 /* Device Configuration Register definitions */ 79 80 #define DEV_CONF_HS_SPEED 0x00000000 81 #define DEV_CONF_LS_SPEED 0x00000002 82 #define DEV_CONF_FS_SPEED 0x00000003 83 #define DEV_CONF_REMWAKEUP 0x00000004 84 #define DEV_CONF_SELFPOW 0x00000008 85 #define DEV_CONF_SYNCFRAME 0x00000010 86 #define DEV_CONF_PHYINT_8 0x00000020 87 #define DEV_CONF_PHYINT_16 0x00000000 88 #define DEV_CONF_UTMI_BIDIR 0x00000040 89 #define DEV_CONF_STATUS_STALL 0x00000080 90 91 /* Device Control Register definitions */ 92 93 #define DEV_CNTL_RESUME 0x00000001 94 #define DEV_CNTL_TFFLUSH 0x00000002 95 #define DEV_CNTL_RXDMAEN 0x00000004 96 #define DEV_CNTL_TXDMAEN 0x00000008 97 #define DEV_CNTL_DESCRUPD 0x00000010 98 #define DEV_CNTL_BIGEND 0x00000020 99 #define DEV_CNTL_BUFFILL 0x00000040 100 #define DEV_CNTL_TSHLDEN 0x00000080 101 #define DEV_CNTL_BURSTEN 0x00000100 102 #define DEV_CNTL_DMAMODE 0x00000200 103 #define DEV_CNTL_SOFTDISCONNECT 0x00000400 104 #define DEV_CNTL_SCALEDOWN 0x00000800 105 #define DEV_CNTL_BURSTLENU 0x00010000 106 #define DEV_CNTL_BURSTLENMSK 0x00ff0000 107 #define DEV_CNTL_TSHLDLENU 0x01000000 108 #define DEV_CNTL_TSHLDLENMSK 0xff000000 109 110 /* Device Status Register definitions */ 111 112 #define DEV_STAT_CFG 0x0000000f 113 #define DEV_STAT_INTF 0x000000f0 114 #define DEV_STAT_ALT 0x00000f00 115 #define DEV_STAT_SUSP 0x00001000 116 #define DEV_STAT_ENUM 0x00006000 117 #define DEV_STAT_ENUM_SPEED_HS 0x00000000 118 #define DEV_STAT_ENUM_SPEED_FS 0x00002000 119 #define DEV_STAT_ENUM_SPEED_LS 0x00004000 120 #define DEV_STAT_RXFIFO_EMPTY 0x00008000 121 #define DEV_STAT_PHY_ERR 0x00010000 122 #define DEV_STAT_TS 0xf0000000 123 124 /* Device Interrupt Register definitions */ 125 126 #define DEV_INT_MSK 0x0000007f 127 #define DEV_INT_SETCFG 0x00000001 128 #define DEV_INT_SETINTF 0x00000002 129 #define DEV_INT_INACTIVE 0x00000004 130 #define DEV_INT_USBRESET 0x00000008 131 #define DEV_INT_SUSPUSB 0x00000010 132 #define DEV_INT_SOF 0x00000020 133 #define DEV_INT_ENUM 0x00000040 134 135 /* Endpoint Interrupt Register definitions */ 136 137 #define ENDP0_INT_CTRLIN 0x00000001 138 #define ENDP1_INT_BULKIN 0x00000002 139 #define ENDP_INT_NONISOIN_MSK 0x0000AAAA 140 #define ENDP2_INT_BULKIN 0x00000004 141 #define ENDP0_INT_CTRLOUT 0x00010000 142 #define ENDP1_INT_BULKOUT 0x00020000 143 #define ENDP2_INT_BULKOUT 0x00040000 144 #define ENDP_INT_NONISOOUT_MSK 0x55540000 145 146 /* Endpoint Register definitions */ 147 #define ENDP_EPDIR_OUT 0x00000000 148 #define ENDP_EPDIR_IN 0x00000010 149 #define ENDP_EPTYPE_CNTL 0x0 150 #define ENDP_EPTYPE_ISO 0x1 151 #define ENDP_EPTYPE_BULK 0x2 152 #define ENDP_EPTYPE_INT 0x3 153 154 /* 155 * Defines for Plug Detect 156 */ 157 158 struct plug_regs { 159 u32 plug_state; 160 u32 plug_pending; 161 }; 162 163 /* Plug State Register definitions */ 164 #define PLUG_STATUS_EN 0x1 165 #define PLUG_STATUS_ATTACHED 0x2 166 #define PLUG_STATUS_PHY_RESET 0x4 167 #define PLUG_STATUS_PHY_MODE 0x8 168 169 /* 170 * Defines for UDC FIFO (Slave Mode) 171 */ 172 struct udcfifo_regs { 173 u32 *fifo_p; 174 }; 175 176 /* 177 * UDC endpoint definitions 178 */ 179 #define UDC_EP0 0 180 #define UDC_EP1 1 181 #define UDC_EP2 2 182 #define UDC_EP3 3 183 184 #endif /* __DW_UDC_H */ 185