1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com 4 */ 5 6 #ifndef _universe_h 7 #define _universe_h 8 9 typedef struct _UNIVERSE UNIVERSE; 10 typedef struct _SLAVE_IMAGE SLAVE_IMAGE; 11 typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET; 12 13 struct _SLAVE_IMAGE { 14 unsigned int ctl; /* Control */ 15 unsigned int bs; /* Base */ 16 unsigned int bd; /* Bound */ 17 unsigned int to; /* Translation */ 18 unsigned int reserved; 19 }; 20 21 struct _UNIVERSE { 22 unsigned int pci_id; 23 unsigned int pci_csr; 24 unsigned int pci_class; 25 unsigned int pci_misc0; 26 unsigned int pci_bs; 27 unsigned int spare0[10]; 28 unsigned int pci_misc1; 29 unsigned int spare1[48]; 30 SLAVE_IMAGE lsi[4]; 31 unsigned int spare2[8]; 32 unsigned int scyc_ctl; 33 unsigned int scyc_addr; 34 unsigned int scyc_en; 35 unsigned int scyc_cmp; 36 unsigned int scyc_swp; 37 unsigned int lmisc; 38 unsigned int slsi; 39 unsigned int l_cmderr; 40 unsigned int laerr; 41 unsigned int spare3[27]; 42 unsigned int dctl; 43 unsigned int dtbc; 44 unsigned int dla; 45 unsigned int spare4[1]; 46 unsigned int dva; 47 unsigned int spare5[1]; 48 unsigned int dcpp; 49 unsigned int spare6[1]; 50 unsigned int dgcs; 51 unsigned int d_llue; 52 unsigned int spare7[54]; 53 unsigned int lint_en; 54 unsigned int lint_stat; 55 unsigned int lint_map0; 56 unsigned int lint_map1; 57 unsigned int vint_en; 58 unsigned int vint_stat; 59 unsigned int vint_map0; 60 unsigned int vint_map1; 61 unsigned int statid; 62 unsigned int vx_statid[7]; 63 unsigned int spare8[48]; 64 unsigned int mast_ctl; 65 unsigned int misc_ctl; 66 unsigned int misc_stat; 67 unsigned int user_am; 68 unsigned int spare9[700]; 69 SLAVE_IMAGE vsi[4]; 70 unsigned int spare10[8]; 71 unsigned int vrai_ctl; 72 unsigned int vrai_bs; 73 unsigned int spare11[2]; 74 unsigned int vcsr_ctl; 75 unsigned int vcsr_to; 76 unsigned int v_amerr; 77 unsigned int vaerr; 78 unsigned int spare12[25]; 79 unsigned int vcsr_clr; 80 unsigned int vcsr_set; 81 unsigned int vcsr_bs; 82 }; 83 84 #define IRQ_VOWN 0x0001 85 #define IRQ_VIRQ1 0x0002 86 #define IRQ_VIRQ2 0x0004 87 #define IRQ_VIRQ3 0x0008 88 #define IRQ_VIRQ4 0x0010 89 #define IRQ_VIRQ5 0x0020 90 #define IRQ_VIRQ6 0x0040 91 #define IRQ_VIRQ7 0x0080 92 #define IRQ_DMA 0x0100 93 #define IRQ_LERR 0x0200 94 #define IRQ_VERR 0x0400 95 #define IRQ_res 0x0800 96 #define IRQ_IACK 0x1000 97 #define IRQ_SWINT 0x2000 98 #define IRQ_SYSFAIL 0x4000 99 #define IRQ_ACFAIL 0x8000 100 101 struct _TDMA_CMD_PACKET { 102 unsigned int dctl; /* DMA Control */ 103 unsigned int dtbc; /* Transfer Byte Count */ 104 unsigned int dlv; /* PCI Address */ 105 unsigned int res1; /* Reserved */ 106 unsigned int dva; /* Vme Address */ 107 unsigned int res2; /* Reserved */ 108 unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */ 109 unsigned int res3; /* Reserved */ 110 }; 111 112 #define VME_AM_A16 0x01 113 #define VME_AM_A24 0x02 114 #define VME_AM_A32 0x03 115 #define VME_AM_Axx 0x03 116 #define VME_AM_SUP 0x04 117 #define VME_AM_DATA 0x10 118 #define VME_AM_PROG 0x20 119 #define VME_AM_Mxx 0x30 120 121 #define VME_FLAG_D8 0x01 122 #define VME_FLAG_D16 0x02 123 #define VME_FLAG_D32 0x03 124 #define VME_FLAG_Dxx 0x03 125 126 #define PCI_MS_MEM 0x01 127 #define PCI_MS_IO 0x02 128 #define PCI_MS_CONFIG 0x03 129 #define PCI_MS_Mxx 0x03 130 131 #endif 132