1 /* 2 * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 #ifndef _universe_h 24 #define _universe_h 25 26 typedef struct _UNIVERSE UNIVERSE; 27 typedef struct _SLAVE_IMAGE SLAVE_IMAGE; 28 typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET; 29 30 struct _SLAVE_IMAGE { 31 unsigned int ctl; /* Control */ 32 unsigned int bs; /* Base */ 33 unsigned int bd; /* Bound */ 34 unsigned int to; /* Translation */ 35 unsigned int reserved; 36 }; 37 38 struct _UNIVERSE { 39 unsigned int pci_id; 40 unsigned int pci_csr; 41 unsigned int pci_class; 42 unsigned int pci_misc0; 43 unsigned int pci_bs; 44 unsigned int spare0[10]; 45 unsigned int pci_misc1; 46 unsigned int spare1[48]; 47 SLAVE_IMAGE lsi[4]; 48 unsigned int spare2[8]; 49 unsigned int scyc_ctl; 50 unsigned int scyc_addr; 51 unsigned int scyc_en; 52 unsigned int scyc_cmp; 53 unsigned int scyc_swp; 54 unsigned int lmisc; 55 unsigned int slsi; 56 unsigned int l_cmderr; 57 unsigned int laerr; 58 unsigned int spare3[27]; 59 unsigned int dctl; 60 unsigned int dtbc; 61 unsigned int dla; 62 unsigned int spare4[1]; 63 unsigned int dva; 64 unsigned int spare5[1]; 65 unsigned int dcpp; 66 unsigned int spare6[1]; 67 unsigned int dgcs; 68 unsigned int d_llue; 69 unsigned int spare7[54]; 70 unsigned int lint_en; 71 unsigned int lint_stat; 72 unsigned int lint_map0; 73 unsigned int lint_map1; 74 unsigned int vint_en; 75 unsigned int vint_stat; 76 unsigned int vint_map0; 77 unsigned int vint_map1; 78 unsigned int statid; 79 unsigned int vx_statid[7]; 80 unsigned int spare8[48]; 81 unsigned int mast_ctl; 82 unsigned int misc_ctl; 83 unsigned int misc_stat; 84 unsigned int user_am; 85 unsigned int spare9[700]; 86 SLAVE_IMAGE vsi[4]; 87 unsigned int spare10[8]; 88 unsigned int vrai_ctl; 89 unsigned int vrai_bs; 90 unsigned int spare11[2]; 91 unsigned int vcsr_ctl; 92 unsigned int vcsr_to; 93 unsigned int v_amerr; 94 unsigned int vaerr; 95 unsigned int spare12[25]; 96 unsigned int vcsr_clr; 97 unsigned int vcsr_set; 98 unsigned int vcsr_bs; 99 }; 100 101 #define IRQ_VOWN 0x0001 102 #define IRQ_VIRQ1 0x0002 103 #define IRQ_VIRQ2 0x0004 104 #define IRQ_VIRQ3 0x0008 105 #define IRQ_VIRQ4 0x0010 106 #define IRQ_VIRQ5 0x0020 107 #define IRQ_VIRQ6 0x0040 108 #define IRQ_VIRQ7 0x0080 109 #define IRQ_DMA 0x0100 110 #define IRQ_LERR 0x0200 111 #define IRQ_VERR 0x0400 112 #define IRQ_res 0x0800 113 #define IRQ_IACK 0x1000 114 #define IRQ_SWINT 0x2000 115 #define IRQ_SYSFAIL 0x4000 116 #define IRQ_ACFAIL 0x8000 117 118 struct _TDMA_CMD_PACKET { 119 unsigned int dctl; /* DMA Control */ 120 unsigned int dtbc; /* Transfer Byte Count */ 121 unsigned int dlv; /* PCI Address */ 122 unsigned int res1; /* Reserved */ 123 unsigned int dva; /* Vme Address */ 124 unsigned int res2; /* Reserved */ 125 unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */ 126 unsigned int res3; /* Reserved */ 127 }; 128 129 #define VME_AM_A16 0x01 130 #define VME_AM_A24 0x02 131 #define VME_AM_A32 0x03 132 #define VME_AM_Axx 0x03 133 #define VME_AM_SUP 0x04 134 #define VME_AM_DATA 0x10 135 #define VME_AM_PROG 0x20 136 #define VME_AM_Mxx 0x30 137 138 #define VME_FLAG_D8 0x01 139 #define VME_FLAG_D16 0x02 140 #define VME_FLAG_D32 0x03 141 #define VME_FLAG_Dxx 0x03 142 143 #define PCI_MS_MEM 0x01 144 #define PCI_MS_IO 0x02 145 #define PCI_MS_CONFIG 0x03 146 #define PCI_MS_Mxx 0x03 147 148 #endif 149