1 /* 2 * tsec.h 3 * 4 * Driver for the Motorola Triple Speed Ethernet Controller 5 * 6 * This software may be used and distributed according to the 7 * terms of the GNU Public License, Version 2, incorporated 8 * herein by reference. 9 * 10 * Copyright 2004, 2007, 2009 Freescale Semiconductor, Inc. 11 * (C) Copyright 2003, Motorola, Inc. 12 * maintained by Xianghua Xiao (x.xiao@motorola.com) 13 * author Andy Fleming 14 * 15 */ 16 17 #ifndef __TSEC_H 18 #define __TSEC_H 19 20 #include <net.h> 21 #include <config.h> 22 23 #define TSEC_SIZE 0x01000 24 #define TSEC_MDIO_OFFSET 0x01000 25 26 #define STD_TSEC_INFO(num) \ 27 { \ 28 .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ 29 .miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR), \ 30 .miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \ 31 + (num - 1) * TSEC_MDIO_OFFSET), \ 32 .devname = CONFIG_TSEC##num##_NAME, \ 33 .phyaddr = TSEC##num##_PHY_ADDR, \ 34 .flags = TSEC##num##_FLAGS \ 35 } 36 37 #define SET_STD_TSEC_INFO(x, num) \ 38 { \ 39 x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ 40 x.miiregs = (tsec_mdio_t *)(MDIO_BASE_ADDR); \ 41 x.miiregs_sgmii = (tsec_mdio_t *)(MDIO_BASE_ADDR \ 42 + (num - 1) * TSEC_MDIO_OFFSET); \ 43 x.devname = CONFIG_TSEC##num##_NAME; \ 44 x.phyaddr = TSEC##num##_PHY_ADDR; \ 45 x.flags = TSEC##num##_FLAGS;\ 46 } 47 48 #define MAC_ADDR_LEN 6 49 50 /* #define TSEC_TIMEOUT 1000000 */ 51 #define TSEC_TIMEOUT 1000 52 #define TOUT_LOOP 1000000 53 54 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ 55 56 /* TBI register addresses */ 57 #define TBI_CR 0x00 58 #define TBI_SR 0x01 59 #define TBI_ANA 0x04 60 #define TBI_ANLPBPA 0x05 61 #define TBI_ANEX 0x06 62 #define TBI_TBICON 0x11 63 64 /* TBI MDIO register bit fields*/ 65 #define TBICON_CLK_SELECT 0x0020 66 #define TBIANA_ASYMMETRIC_PAUSE 0x0100 67 #define TBIANA_SYMMETRIC_PAUSE 0x0080 68 #define TBIANA_HALF_DUPLEX 0x0040 69 #define TBIANA_FULL_DUPLEX 0x0020 70 #define TBICR_PHY_RESET 0x8000 71 #define TBICR_ANEG_ENABLE 0x1000 72 #define TBICR_RESTART_ANEG 0x0200 73 #define TBICR_FULL_DUPLEX 0x0100 74 #define TBICR_SPEED1_SET 0x0040 75 76 77 /* MAC register bits */ 78 #define MACCFG1_SOFT_RESET 0x80000000 79 #define MACCFG1_RESET_RX_MC 0x00080000 80 #define MACCFG1_RESET_TX_MC 0x00040000 81 #define MACCFG1_RESET_RX_FUN 0x00020000 82 #define MACCFG1_RESET_TX_FUN 0x00010000 83 #define MACCFG1_LOOPBACK 0x00000100 84 #define MACCFG1_RX_FLOW 0x00000020 85 #define MACCFG1_TX_FLOW 0x00000010 86 #define MACCFG1_SYNCD_RX_EN 0x00000008 87 #define MACCFG1_RX_EN 0x00000004 88 #define MACCFG1_SYNCD_TX_EN 0x00000002 89 #define MACCFG1_TX_EN 0x00000001 90 91 #define MACCFG2_INIT_SETTINGS 0x00007205 92 #define MACCFG2_FULL_DUPLEX 0x00000001 93 #define MACCFG2_IF 0x00000300 94 #define MACCFG2_GMII 0x00000200 95 #define MACCFG2_MII 0x00000100 96 97 #define ECNTRL_INIT_SETTINGS 0x00001000 98 #define ECNTRL_TBI_MODE 0x00000020 99 #define ECNTRL_R100 0x00000008 100 #define ECNTRL_SGMII_MODE 0x00000002 101 102 #define miim_end -2 103 #define miim_read -1 104 105 #ifndef CONFIG_SYS_TBIPA_VALUE 106 #define CONFIG_SYS_TBIPA_VALUE 0x1f 107 #endif 108 #define MIIMCFG_INIT_VALUE 0x00000003 109 #define MIIMCFG_RESET 0x80000000 110 111 #define MIIMIND_BUSY 0x00000001 112 #define MIIMIND_NOTVALID 0x00000004 113 114 #define MIIM_CONTROL 0x00 115 #define MIIM_CONTROL_RESET 0x00009140 116 #define MIIM_CONTROL_INIT 0x00001140 117 #define MIIM_CONTROL_RESTART 0x00001340 118 #define MIIM_ANEN 0x00001000 119 120 #define MIIM_CR 0x00 121 #define MIIM_CR_RST 0x00008000 122 #define MIIM_CR_INIT 0x00001000 123 124 #define MIIM_STATUS 0x1 125 #define MIIM_STATUS_AN_DONE 0x00000020 126 #define MIIM_STATUS_LINK 0x0004 127 #define PHY_BMSR_AUTN_ABLE 0x0008 128 #define PHY_BMSR_AUTN_COMP 0x0020 129 130 #define MIIM_PHYIR1 0x2 131 #define MIIM_PHYIR2 0x3 132 133 #define MIIM_ANAR 0x4 134 #define MIIM_ANAR_INIT 0x1e1 135 136 #define MIIM_TBI_ANLPBPA 0x5 137 #define MIIM_TBI_ANLPBPA_HALF 0x00000040 138 #define MIIM_TBI_ANLPBPA_FULL 0x00000020 139 140 #define MIIM_TBI_ANEX 0x6 141 #define MIIM_TBI_ANEX_NP 0x00000004 142 #define MIIM_TBI_ANEX_PRX 0x00000002 143 144 #define MIIM_GBIT_CONTROL 0x9 145 #define MIIM_GBIT_CONTROL_INIT 0xe00 146 147 #define MIIM_EXT_PAGE_ACCESS 0x1f 148 149 /* Broadcom BCM54xx -- taken from linux sungem_phy */ 150 #define MIIM_BCM54xx_AUXCNTL 0x18 151 #define MIIM_BCM54xx_AUXCNTL_ENCODE(val) ((val & 0x7) << 12)|(val & 0x7) 152 #define MIIM_BCM54xx_AUXSTATUS 0x19 153 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 154 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 155 156 #define MIIM_BCM54XX_SHD 0x1c /* 0x1c shadow registers */ 157 #define MIIM_BCM54XX_SHD_WRITE 0x8000 158 #define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) 159 #define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) 160 #define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \ 161 (MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \ 162 MIIM_BCM54XX_SHD_DATA(data)) 163 164 #define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ 165 #define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ 166 #define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ 167 #define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ 168 169 /* Cicada Auxiliary Control/Status Register */ 170 #define MIIM_CIS8201_AUX_CONSTAT 0x1c 171 #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004 172 #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020 173 #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018 174 #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010 175 #define MIIM_CIS8201_AUXCONSTAT_100 0x0008 176 177 /* Cicada Extended Control Register 1 */ 178 #define MIIM_CIS8201_EXT_CON1 0x17 179 #define MIIM_CIS8201_EXTCON1_INIT 0x0000 180 181 /* Cicada 8204 Extended PHY Control Register 1 */ 182 #define MIIM_CIS8204_EPHY_CON 0x17 183 #define MIIM_CIS8204_EPHYCON_INIT 0x0006 184 #define MIIM_CIS8204_EPHYCON_RGMII 0x1100 185 186 /* Cicada 8204 Serial LED Control Register */ 187 #define MIIM_CIS8204_SLED_CON 0x1b 188 #define MIIM_CIS8204_SLEDCON_INIT 0x1115 189 190 #define MIIM_GBIT_CON 0x09 191 #define MIIM_GBIT_CON_ADVERT 0x0e00 192 193 /* Entry for Vitesse VSC8244 regs starts here */ 194 /* Vitesse VSC8244 Auxiliary Control/Status Register */ 195 #define MIIM_VSC8244_AUX_CONSTAT 0x1c 196 #define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000 197 #define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020 198 #define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018 199 #define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010 200 #define MIIM_VSC8244_AUXCONSTAT_100 0x0008 201 #define MIIM_CONTROL_INIT_LOOPBACK 0x4000 202 203 /* Vitesse VSC8244 Extended PHY Control Register 1 */ 204 #define MIIM_VSC8244_EPHY_CON 0x17 205 #define MIIM_VSC8244_EPHYCON_INIT 0x0006 206 207 /* Vitesse VSC8244 Serial LED Control Register */ 208 #define MIIM_VSC8244_LED_CON 0x1b 209 #define MIIM_VSC8244_LEDCON_INIT 0xF011 210 211 /* Entry for Vitesse VSC8601 regs starts here (Not complete) */ 212 /* Vitesse VSC8601 Extended PHY Control Register 1 */ 213 #define MIIM_VSC8601_EPHY_CON 0x17 214 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120 215 #define MIIM_VSC8601_SKEW_CTRL 0x1c 216 217 /* 88E1011 PHY Status Register */ 218 #define MIIM_88E1011_PHY_STATUS 0x11 219 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000 220 #define MIIM_88E1011_PHYSTAT_GBIT 0x8000 221 #define MIIM_88E1011_PHYSTAT_100 0x4000 222 #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 223 #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 224 #define MIIM_88E1011_PHYSTAT_LINK 0x0400 225 226 #define MIIM_88E1011_PHY_SCR 0x10 227 #define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 228 229 /* 88E1111 PHY LED Control Register */ 230 #define MIIM_88E1111_PHY_LED_CONTROL 24 231 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100 232 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C 233 234 /* 88E1121 PHY LED Control Register */ 235 #define MIIM_88E1121_PHY_LED_CTRL 16 236 #define MIIM_88E1121_PHY_LED_PAGE 3 237 #define MIIM_88E1121_PHY_LED_DEF 0x0030 238 239 /* 88E1121 PHY IRQ Enable/Status Register */ 240 #define MIIM_88E1121_PHY_IRQ_EN 18 241 #define MIIM_88E1121_PHY_IRQ_STATUS 19 242 243 #define MIIM_88E1121_PHY_PAGE 22 244 245 /* 88E1145 Extended PHY Specific Control Register */ 246 #define MIIM_88E1145_PHY_EXT_CR 20 247 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 248 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 249 250 #define MIIM_88E1145_PHY_PAGE 29 251 #define MIIM_88E1145_PHY_CAL_OV 30 252 253 /* RTL8211B PHY Status Register */ 254 #define MIIM_RTL8211B_PHY_STATUS 0x11 255 #define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000 256 #define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000 257 #define MIIM_RTL8211B_PHYSTAT_100 0x4000 258 #define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000 259 #define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800 260 #define MIIM_RTL8211B_PHYSTAT_LINK 0x0400 261 262 /* DM9161 Control register values */ 263 #define MIIM_DM9161_CR_STOP 0x0400 264 #define MIIM_DM9161_CR_RSTAN 0x1200 265 266 #define MIIM_DM9161_SCR 0x10 267 #define MIIM_DM9161_SCR_INIT 0x0610 268 269 /* DM9161 Specified Configuration and Status Register */ 270 #define MIIM_DM9161_SCSR 0x11 271 #define MIIM_DM9161_SCSR_100F 0x8000 272 #define MIIM_DM9161_SCSR_100H 0x4000 273 #define MIIM_DM9161_SCSR_10F 0x2000 274 #define MIIM_DM9161_SCSR_10H 0x1000 275 276 /* DM9161 10BT Configuration/Status */ 277 #define MIIM_DM9161_10BTCSR 0x12 278 #define MIIM_DM9161_10BTCSR_INIT 0x7800 279 280 /* LXT971 Status 2 registers */ 281 #define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ 282 #define MIIM_LXT971_SR2_SPEED_MASK 0x4200 283 #define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ 284 #define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ 285 #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ 286 #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ 287 288 /* DP83865 Control register values */ 289 #define MIIM_DP83865_CR_INIT 0x9200 290 291 /* DP83865 Link and Auto-Neg Status Register */ 292 #define MIIM_DP83865_LANR 0x11 293 #define MIIM_DP83865_SPD_MASK 0x0018 294 #define MIIM_DP83865_SPD_1000 0x0010 295 #define MIIM_DP83865_SPD_100 0x0008 296 #define MIIM_DP83865_DPX_FULL 0x0002 297 298 #define MIIM_READ_COMMAND 0x00000001 299 300 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN 301 302 #define MINFLR_INIT_SETTINGS 0x00000040 303 304 #define DMACTRL_INIT_SETTINGS 0x000000c3 305 #define DMACTRL_GRS 0x00000010 306 #define DMACTRL_GTS 0x00000008 307 308 #define TSTAT_CLEAR_THALT 0x80000000 309 #define RSTAT_CLEAR_RHALT 0x00800000 310 311 312 #define IEVENT_INIT_CLEAR 0xffffffff 313 #define IEVENT_BABR 0x80000000 314 #define IEVENT_RXC 0x40000000 315 #define IEVENT_BSY 0x20000000 316 #define IEVENT_EBERR 0x10000000 317 #define IEVENT_MSRO 0x04000000 318 #define IEVENT_GTSC 0x02000000 319 #define IEVENT_BABT 0x01000000 320 #define IEVENT_TXC 0x00800000 321 #define IEVENT_TXE 0x00400000 322 #define IEVENT_TXB 0x00200000 323 #define IEVENT_TXF 0x00100000 324 #define IEVENT_IE 0x00080000 325 #define IEVENT_LC 0x00040000 326 #define IEVENT_CRL 0x00020000 327 #define IEVENT_XFUN 0x00010000 328 #define IEVENT_RXB0 0x00008000 329 #define IEVENT_GRSC 0x00000100 330 #define IEVENT_RXF0 0x00000080 331 332 #define IMASK_INIT_CLEAR 0x00000000 333 #define IMASK_TXEEN 0x00400000 334 #define IMASK_TXBEN 0x00200000 335 #define IMASK_TXFEN 0x00100000 336 #define IMASK_RXFEN0 0x00000080 337 338 339 /* Default Attribute fields */ 340 #define ATTR_INIT_SETTINGS 0x000000c0 341 #define ATTRELI_INIT_SETTINGS 0x00000000 342 343 344 /* TxBD status field bits */ 345 #define TXBD_READY 0x8000 346 #define TXBD_PADCRC 0x4000 347 #define TXBD_WRAP 0x2000 348 #define TXBD_INTERRUPT 0x1000 349 #define TXBD_LAST 0x0800 350 #define TXBD_CRC 0x0400 351 #define TXBD_DEF 0x0200 352 #define TXBD_HUGEFRAME 0x0080 353 #define TXBD_LATECOLLISION 0x0080 354 #define TXBD_RETRYLIMIT 0x0040 355 #define TXBD_RETRYCOUNTMASK 0x003c 356 #define TXBD_UNDERRUN 0x0002 357 #define TXBD_STATS 0x03ff 358 359 /* RxBD status field bits */ 360 #define RXBD_EMPTY 0x8000 361 #define RXBD_RO1 0x4000 362 #define RXBD_WRAP 0x2000 363 #define RXBD_INTERRUPT 0x1000 364 #define RXBD_LAST 0x0800 365 #define RXBD_FIRST 0x0400 366 #define RXBD_MISS 0x0100 367 #define RXBD_BROADCAST 0x0080 368 #define RXBD_MULTICAST 0x0040 369 #define RXBD_LARGE 0x0020 370 #define RXBD_NONOCTET 0x0010 371 #define RXBD_SHORT 0x0008 372 #define RXBD_CRCERR 0x0004 373 #define RXBD_OVERRUN 0x0002 374 #define RXBD_TRUNCATED 0x0001 375 #define RXBD_STATS 0x003f 376 377 typedef struct txbd8 378 { 379 ushort status; /* Status Fields */ 380 ushort length; /* Buffer length */ 381 uint bufPtr; /* Buffer Pointer */ 382 } txbd8_t; 383 384 typedef struct rxbd8 385 { 386 ushort status; /* Status Fields */ 387 ushort length; /* Buffer Length */ 388 uint bufPtr; /* Buffer Pointer */ 389 } rxbd8_t; 390 391 typedef struct rmon_mib 392 { 393 /* Transmit and Receive Counters */ 394 uint tr64; /* Transmit and Receive 64-byte Frame Counter */ 395 uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */ 396 uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */ 397 uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */ 398 uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */ 399 uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */ 400 uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */ 401 /* Receive Counters */ 402 uint rbyt; /* Receive Byte Counter */ 403 uint rpkt; /* Receive Packet Counter */ 404 uint rfcs; /* Receive FCS Error Counter */ 405 uint rmca; /* Receive Multicast Packet (Counter) */ 406 uint rbca; /* Receive Broadcast Packet */ 407 uint rxcf; /* Receive Control Frame Packet */ 408 uint rxpf; /* Receive Pause Frame Packet */ 409 uint rxuo; /* Receive Unknown OP Code */ 410 uint raln; /* Receive Alignment Error */ 411 uint rflr; /* Receive Frame Length Error */ 412 uint rcde; /* Receive Code Error */ 413 uint rcse; /* Receive Carrier Sense Error */ 414 uint rund; /* Receive Undersize Packet */ 415 uint rovr; /* Receive Oversize Packet */ 416 uint rfrg; /* Receive Fragments */ 417 uint rjbr; /* Receive Jabber */ 418 uint rdrp; /* Receive Drop */ 419 /* Transmit Counters */ 420 uint tbyt; /* Transmit Byte Counter */ 421 uint tpkt; /* Transmit Packet */ 422 uint tmca; /* Transmit Multicast Packet */ 423 uint tbca; /* Transmit Broadcast Packet */ 424 uint txpf; /* Transmit Pause Control Frame */ 425 uint tdfr; /* Transmit Deferral Packet */ 426 uint tedf; /* Transmit Excessive Deferral Packet */ 427 uint tscl; /* Transmit Single Collision Packet */ 428 /* (0x2_n700) */ 429 uint tmcl; /* Transmit Multiple Collision Packet */ 430 uint tlcl; /* Transmit Late Collision Packet */ 431 uint txcl; /* Transmit Excessive Collision Packet */ 432 uint tncl; /* Transmit Total Collision */ 433 434 uint res2; 435 436 uint tdrp; /* Transmit Drop Frame */ 437 uint tjbr; /* Transmit Jabber Frame */ 438 uint tfcs; /* Transmit FCS Error */ 439 uint txcf; /* Transmit Control Frame */ 440 uint tovr; /* Transmit Oversize Frame */ 441 uint tund; /* Transmit Undersize Frame */ 442 uint tfrg; /* Transmit Fragments Frame */ 443 /* General Registers */ 444 uint car1; /* Carry Register One */ 445 uint car2; /* Carry Register Two */ 446 uint cam1; /* Carry Register One Mask */ 447 uint cam2; /* Carry Register Two Mask */ 448 } rmon_mib_t; 449 450 typedef struct tsec_hash_regs 451 { 452 uint iaddr0; /* Individual Address Register 0 */ 453 uint iaddr1; /* Individual Address Register 1 */ 454 uint iaddr2; /* Individual Address Register 2 */ 455 uint iaddr3; /* Individual Address Register 3 */ 456 uint iaddr4; /* Individual Address Register 4 */ 457 uint iaddr5; /* Individual Address Register 5 */ 458 uint iaddr6; /* Individual Address Register 6 */ 459 uint iaddr7; /* Individual Address Register 7 */ 460 uint res1[24]; 461 uint gaddr0; /* Group Address Register 0 */ 462 uint gaddr1; /* Group Address Register 1 */ 463 uint gaddr2; /* Group Address Register 2 */ 464 uint gaddr3; /* Group Address Register 3 */ 465 uint gaddr4; /* Group Address Register 4 */ 466 uint gaddr5; /* Group Address Register 5 */ 467 uint gaddr6; /* Group Address Register 6 */ 468 uint gaddr7; /* Group Address Register 7 */ 469 uint res2[24]; 470 } tsec_hash_t; 471 472 typedef struct tsec_mdio { 473 uint res1[4]; 474 uint ieventm; 475 uint imaskm; 476 uint res2; 477 uint emapm; 478 uint res3[320]; 479 uint miimcfg; /* MII Management: Configuration */ 480 uint miimcom; /* MII Management: Command */ 481 uint miimadd; /* MII Management: Address */ 482 uint miimcon; /* MII Management: Control */ 483 uint miimstat; /* MII Management: Status */ 484 uint miimind; /* MII Management: Indicators */ 485 uint res4[690]; 486 } tsec_mdio_t; 487 488 typedef struct tsec 489 { 490 /* General Control and Status Registers (0x2_n000) */ 491 uint res000[4]; 492 493 uint ievent; /* Interrupt Event */ 494 uint imask; /* Interrupt Mask */ 495 uint edis; /* Error Disabled */ 496 uint res01c; 497 uint ecntrl; /* Ethernet Control */ 498 uint minflr; /* Minimum Frame Length */ 499 uint ptv; /* Pause Time Value */ 500 uint dmactrl; /* DMA Control */ 501 uint tbipa; /* TBI PHY Address */ 502 503 uint res034[3]; 504 uint res040[48]; 505 506 /* Transmit Control and Status Registers (0x2_n100) */ 507 uint tctrl; /* Transmit Control */ 508 uint tstat; /* Transmit Status */ 509 uint res108; 510 uint tbdlen; /* Tx BD Data Length */ 511 uint res110[5]; 512 uint ctbptr; /* Current TxBD Pointer */ 513 uint res128[23]; 514 uint tbptr; /* TxBD Pointer */ 515 uint res188[30]; 516 /* (0x2_n200) */ 517 uint res200; 518 uint tbase; /* TxBD Base Address */ 519 uint res208[42]; 520 uint ostbd; /* Out of Sequence TxBD */ 521 uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ 522 uint res2b8[18]; 523 524 /* Receive Control and Status Registers (0x2_n300) */ 525 uint rctrl; /* Receive Control */ 526 uint rstat; /* Receive Status */ 527 uint res308; 528 uint rbdlen; /* RxBD Data Length */ 529 uint res310[4]; 530 uint res320; 531 uint crbptr; /* Current Receive Buffer Pointer */ 532 uint res328[6]; 533 uint mrblr; /* Maximum Receive Buffer Length */ 534 uint res344[16]; 535 uint rbptr; /* RxBD Pointer */ 536 uint res388[30]; 537 /* (0x2_n400) */ 538 uint res400; 539 uint rbase; /* RxBD Base Address */ 540 uint res408[62]; 541 542 /* MAC Registers (0x2_n500) */ 543 uint maccfg1; /* MAC Configuration #1 */ 544 uint maccfg2; /* MAC Configuration #2 */ 545 uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */ 546 uint hafdup; /* Half-duplex */ 547 uint maxfrm; /* Maximum Frame */ 548 uint res514; 549 uint res518; 550 551 uint res51c; 552 553 uint resmdio[6]; 554 555 uint res538; 556 557 uint ifstat; /* Interface Status */ 558 uint macstnaddr1; /* Station Address, part 1 */ 559 uint macstnaddr2; /* Station Address, part 2 */ 560 uint res548[46]; 561 562 /* (0x2_n600) */ 563 uint res600[32]; 564 565 /* RMON MIB Registers (0x2_n680-0x2_n73c) */ 566 rmon_mib_t rmon; 567 uint res740[48]; 568 569 /* Hash Function Registers (0x2_n800) */ 570 tsec_hash_t hash; 571 572 uint res900[128]; 573 574 /* Pattern Registers (0x2_nb00) */ 575 uint resb00[62]; 576 uint attr; /* Default Attribute Register */ 577 uint attreli; /* Default Attribute Extract Length and Index */ 578 579 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ 580 uint resc00[256]; 581 } tsec_t; 582 583 #define TSEC_GIGABIT (1) 584 585 /* This flag currently only has 586 * meaning if we're using the eTSEC */ 587 #define TSEC_REDUCED (1 << 1) /* MAC-PHY interface uses RGMII */ 588 #define TSEC_SGMII (1 << 2) /* MAC-PHY interface uses SGMII */ 589 #define TSEC_FIBER (1 << 3) /* PHY uses fiber, eg 1000 Base-X */ 590 591 struct tsec_private { 592 volatile tsec_t *regs; 593 volatile tsec_mdio_t *phyregs; 594 volatile tsec_mdio_t *phyregs_sgmii; 595 struct phy_info *phyinfo; 596 uint phyaddr; 597 u32 flags; 598 uint link; 599 uint duplexity; 600 uint speed; 601 }; 602 603 604 /* 605 * struct phy_cmd: A command for reading or writing a PHY register 606 * 607 * mii_reg: The register to read or write 608 * 609 * mii_data: For writes, the value to put in the register. 610 * A value of -1 indicates this is a read. 611 * 612 * funct: A function pointer which is invoked for each command. 613 * For reads, this function will be passed the value read 614 * from the PHY, and process it. 615 * For writes, the result of this function will be written 616 * to the PHY register 617 */ 618 struct phy_cmd { 619 uint mii_reg; 620 uint mii_data; 621 uint (*funct) (uint mii_reg, struct tsec_private * priv); 622 }; 623 624 /* struct phy_info: a structure which defines attributes for a PHY 625 * 626 * id will contain a number which represents the PHY. During 627 * startup, the driver will poll the PHY to find out what its 628 * UID--as defined by registers 2 and 3--is. The 32-bit result 629 * gotten from the PHY will be shifted right by "shift" bits to 630 * discard any bits which may change based on revision numbers 631 * unimportant to functionality 632 * 633 * The struct phy_cmd entries represent pointers to an arrays of 634 * commands which tell the driver what to do to the PHY. 635 */ 636 struct phy_info { 637 uint id; 638 char *name; 639 uint shift; 640 /* Called to configure the PHY, and modify the controller 641 * based on the results */ 642 struct phy_cmd *config; 643 644 /* Called when starting up the controller */ 645 struct phy_cmd *startup; 646 647 /* Called when bringing down the controller */ 648 struct phy_cmd *shutdown; 649 }; 650 651 struct tsec_info_struct { 652 tsec_t *regs; 653 tsec_mdio_t *miiregs; 654 tsec_mdio_t *miiregs_sgmii; 655 char *devname; 656 unsigned int phyaddr; 657 u32 flags; 658 }; 659 660 int tsec_standard_init(bd_t *bis); 661 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num); 662 663 #endif /* __TSEC_H */ 664