1 /* 2 * tsec.h 3 * 4 * Driver for the Motorola Triple Speed Ethernet Controller 5 * 6 * This software may be used and distributed according to the 7 * terms of the GNU Public License, Version 2, incorporated 8 * herein by reference. 9 * 10 * Copyright 2004, 2007 Freescale Semiconductor, Inc. 11 * (C) Copyright 2003, Motorola, Inc. 12 * maintained by Xianghua Xiao (x.xiao@motorola.com) 13 * author Andy Fleming 14 * 15 */ 16 17 #ifndef __TSEC_H 18 #define __TSEC_H 19 20 #include <net.h> 21 #include <config.h> 22 23 #ifndef CFG_TSEC1_OFFSET 24 #define CFG_TSEC1_OFFSET (0x24000) 25 #endif 26 27 #define TSEC_SIZE 0x01000 28 29 /* FIXME: Should these be pushed back to 83xx and 85xx config files? */ 30 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ 31 || defined(CONFIG_MPC83XX) 32 #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET) 33 #endif 34 35 #define STD_TSEC_INFO(num) \ 36 { \ 37 .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ 38 .miiregs = (tsec_t *)TSEC_BASE_ADDR, \ 39 .devname = CONFIG_TSEC##num##_NAME, \ 40 .phyaddr = TSEC##num##_PHY_ADDR, \ 41 .flags = TSEC##num##_FLAGS \ 42 } 43 44 #define SET_STD_TSEC_INFO(x, num) \ 45 { \ 46 x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ 47 x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \ 48 x.devname = CONFIG_TSEC##num##_NAME; \ 49 x.phyaddr = TSEC##num##_PHY_ADDR; \ 50 x.flags = TSEC##num##_FLAGS;\ 51 } 52 53 54 55 #define MAC_ADDR_LEN 6 56 57 /* #define TSEC_TIMEOUT 1000000 */ 58 #define TSEC_TIMEOUT 1000 59 #define TOUT_LOOP 1000000 60 61 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ 62 63 /* TBI register addresses */ 64 #define TBI_CR 0x00 65 #define TBI_SR 0x01 66 #define TBI_ANA 0x04 67 #define TBI_ANLPBPA 0x05 68 #define TBI_ANEX 0x06 69 #define TBI_TBICON 0x11 70 71 /* TBI MDIO register bit fields*/ 72 #define TBICON_CLK_SELECT 0x0020 73 #define TBIANA_ASYMMETRIC_PAUSE 0x0100 74 #define TBIANA_SYMMETRIC_PAUSE 0x0080 75 #define TBIANA_HALF_DUPLEX 0x0040 76 #define TBIANA_FULL_DUPLEX 0x0020 77 #define TBICR_PHY_RESET 0x8000 78 #define TBICR_ANEG_ENABLE 0x1000 79 #define TBICR_RESTART_ANEG 0x0200 80 #define TBICR_FULL_DUPLEX 0x0100 81 #define TBICR_SPEED1_SET 0x0040 82 83 84 /* MAC register bits */ 85 #define MACCFG1_SOFT_RESET 0x80000000 86 #define MACCFG1_RESET_RX_MC 0x00080000 87 #define MACCFG1_RESET_TX_MC 0x00040000 88 #define MACCFG1_RESET_RX_FUN 0x00020000 89 #define MACCFG1_RESET_TX_FUN 0x00010000 90 #define MACCFG1_LOOPBACK 0x00000100 91 #define MACCFG1_RX_FLOW 0x00000020 92 #define MACCFG1_TX_FLOW 0x00000010 93 #define MACCFG1_SYNCD_RX_EN 0x00000008 94 #define MACCFG1_RX_EN 0x00000004 95 #define MACCFG1_SYNCD_TX_EN 0x00000002 96 #define MACCFG1_TX_EN 0x00000001 97 98 #define MACCFG2_INIT_SETTINGS 0x00007205 99 #define MACCFG2_FULL_DUPLEX 0x00000001 100 #define MACCFG2_IF 0x00000300 101 #define MACCFG2_GMII 0x00000200 102 #define MACCFG2_MII 0x00000100 103 104 #define ECNTRL_INIT_SETTINGS 0x00001000 105 #define ECNTRL_TBI_MODE 0x00000020 106 #define ECNTRL_R100 0x00000008 107 #define ECNTRL_SGMII_MODE 0x00000002 108 109 #define miim_end -2 110 #define miim_read -1 111 112 #ifndef CFG_TBIPA_VALUE 113 #define CFG_TBIPA_VALUE 0x1f 114 #endif 115 #define MIIMCFG_INIT_VALUE 0x00000003 116 #define MIIMCFG_RESET 0x80000000 117 118 #define MIIMIND_BUSY 0x00000001 119 #define MIIMIND_NOTVALID 0x00000004 120 121 #define MIIM_CONTROL 0x00 122 #define MIIM_CONTROL_RESET 0x00009140 123 #define MIIM_CONTROL_INIT 0x00001140 124 #define MIIM_CONTROL_RESTART 0x00001340 125 #define MIIM_ANEN 0x00001000 126 127 #define MIIM_CR 0x00 128 #define MIIM_CR_RST 0x00008000 129 #define MIIM_CR_INIT 0x00001000 130 131 #define MIIM_STATUS 0x1 132 #define MIIM_STATUS_AN_DONE 0x00000020 133 #define MIIM_STATUS_LINK 0x0004 134 #define PHY_BMSR_AUTN_ABLE 0x0008 135 #define PHY_BMSR_AUTN_COMP 0x0020 136 137 #define MIIM_PHYIR1 0x2 138 #define MIIM_PHYIR2 0x3 139 140 #define MIIM_ANAR 0x4 141 #define MIIM_ANAR_INIT 0x1e1 142 143 #define MIIM_TBI_ANLPBPA 0x5 144 #define MIIM_TBI_ANLPBPA_HALF 0x00000040 145 #define MIIM_TBI_ANLPBPA_FULL 0x00000020 146 147 #define MIIM_TBI_ANEX 0x6 148 #define MIIM_TBI_ANEX_NP 0x00000004 149 #define MIIM_TBI_ANEX_PRX 0x00000002 150 151 #define MIIM_GBIT_CONTROL 0x9 152 #define MIIM_GBIT_CONTROL_INIT 0xe00 153 154 #define MIIM_EXT_PAGE_ACCESS 0x1f 155 156 /* Broadcom BCM54xx -- taken from linux sungem_phy */ 157 #define MIIM_BCM54xx_AUXSTATUS 0x19 158 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 159 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 160 161 /* Cicada Auxiliary Control/Status Register */ 162 #define MIIM_CIS8201_AUX_CONSTAT 0x1c 163 #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004 164 #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020 165 #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018 166 #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010 167 #define MIIM_CIS8201_AUXCONSTAT_100 0x0008 168 169 /* Cicada Extended Control Register 1 */ 170 #define MIIM_CIS8201_EXT_CON1 0x17 171 #define MIIM_CIS8201_EXTCON1_INIT 0x0000 172 173 /* Cicada 8204 Extended PHY Control Register 1 */ 174 #define MIIM_CIS8204_EPHY_CON 0x17 175 #define MIIM_CIS8204_EPHYCON_INIT 0x0006 176 #define MIIM_CIS8204_EPHYCON_RGMII 0x1100 177 178 /* Cicada 8204 Serial LED Control Register */ 179 #define MIIM_CIS8204_SLED_CON 0x1b 180 #define MIIM_CIS8204_SLEDCON_INIT 0x1115 181 182 #define MIIM_GBIT_CON 0x09 183 #define MIIM_GBIT_CON_ADVERT 0x0e00 184 185 /* Entry for Vitesse VSC8244 regs starts here */ 186 /* Vitesse VSC8244 Auxiliary Control/Status Register */ 187 #define MIIM_VSC8244_AUX_CONSTAT 0x1c 188 #define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000 189 #define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020 190 #define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018 191 #define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010 192 #define MIIM_VSC8244_AUXCONSTAT_100 0x0008 193 #define MIIM_CONTROL_INIT_LOOPBACK 0x4000 194 195 /* Vitesse VSC8244 Extended PHY Control Register 1 */ 196 #define MIIM_VSC8244_EPHY_CON 0x17 197 #define MIIM_VSC8244_EPHYCON_INIT 0x0006 198 199 /* Vitesse VSC8244 Serial LED Control Register */ 200 #define MIIM_VSC8244_LED_CON 0x1b 201 #define MIIM_VSC8244_LEDCON_INIT 0xF011 202 203 /* Entry for Vitesse VSC8601 regs starts here (Not complete) */ 204 /* Vitesse VSC8601 Extended PHY Control Register 1 */ 205 #define MIIM_VSC8601_EPHY_CON 0x17 206 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120 207 #define MIIM_VSC8601_SKEW_CTRL 0x1c 208 209 /* 88E1011 PHY Status Register */ 210 #define MIIM_88E1011_PHY_STATUS 0x11 211 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000 212 #define MIIM_88E1011_PHYSTAT_GBIT 0x8000 213 #define MIIM_88E1011_PHYSTAT_100 0x4000 214 #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 215 #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 216 #define MIIM_88E1011_PHYSTAT_LINK 0x0400 217 218 #define MIIM_88E1011_PHY_SCR 0x10 219 #define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 220 221 /* 88E1111 PHY LED Control Register */ 222 #define MIIM_88E1111_PHY_LED_CONTROL 24 223 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100 224 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C 225 226 /* 88E1121 PHY LED Control Register */ 227 #define MIIM_88E1121_PHY_LED_CTRL 16 228 #define MIIM_88E1121_PHY_LED_PAGE 3 229 #define MIIM_88E1121_PHY_LED_DEF 0x0030 230 231 #define MIIM_88E1121_PHY_PAGE 22 232 233 /* 88E1145 Extended PHY Specific Control Register */ 234 #define MIIM_88E1145_PHY_EXT_CR 20 235 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 236 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 237 238 #define MIIM_88E1145_PHY_PAGE 29 239 #define MIIM_88E1145_PHY_CAL_OV 30 240 241 /* RTL8211B PHY Status Register */ 242 #define MIIM_RTL8211B_PHY_STATUS 0x11 243 #define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000 244 #define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000 245 #define MIIM_RTL8211B_PHYSTAT_100 0x4000 246 #define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000 247 #define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800 248 #define MIIM_RTL8211B_PHYSTAT_LINK 0x0400 249 250 /* DM9161 Control register values */ 251 #define MIIM_DM9161_CR_STOP 0x0400 252 #define MIIM_DM9161_CR_RSTAN 0x1200 253 254 #define MIIM_DM9161_SCR 0x10 255 #define MIIM_DM9161_SCR_INIT 0x0610 256 257 /* DM9161 Specified Configuration and Status Register */ 258 #define MIIM_DM9161_SCSR 0x11 259 #define MIIM_DM9161_SCSR_100F 0x8000 260 #define MIIM_DM9161_SCSR_100H 0x4000 261 #define MIIM_DM9161_SCSR_10F 0x2000 262 #define MIIM_DM9161_SCSR_10H 0x1000 263 264 /* DM9161 10BT Configuration/Status */ 265 #define MIIM_DM9161_10BTCSR 0x12 266 #define MIIM_DM9161_10BTCSR_INIT 0x7800 267 268 /* LXT971 Status 2 registers */ 269 #define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ 270 #define MIIM_LXT971_SR2_SPEED_MASK 0x4200 271 #define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ 272 #define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ 273 #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ 274 #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ 275 276 /* DP83865 Control register values */ 277 #define MIIM_DP83865_CR_INIT 0x9200 278 279 /* DP83865 Link and Auto-Neg Status Register */ 280 #define MIIM_DP83865_LANR 0x11 281 #define MIIM_DP83865_SPD_MASK 0x0018 282 #define MIIM_DP83865_SPD_1000 0x0010 283 #define MIIM_DP83865_SPD_100 0x0008 284 #define MIIM_DP83865_DPX_FULL 0x0002 285 286 #define MIIM_READ_COMMAND 0x00000001 287 288 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN 289 290 #define MINFLR_INIT_SETTINGS 0x00000040 291 292 #define DMACTRL_INIT_SETTINGS 0x000000c3 293 #define DMACTRL_GRS 0x00000010 294 #define DMACTRL_GTS 0x00000008 295 296 #define TSTAT_CLEAR_THALT 0x80000000 297 #define RSTAT_CLEAR_RHALT 0x00800000 298 299 300 #define IEVENT_INIT_CLEAR 0xffffffff 301 #define IEVENT_BABR 0x80000000 302 #define IEVENT_RXC 0x40000000 303 #define IEVENT_BSY 0x20000000 304 #define IEVENT_EBERR 0x10000000 305 #define IEVENT_MSRO 0x04000000 306 #define IEVENT_GTSC 0x02000000 307 #define IEVENT_BABT 0x01000000 308 #define IEVENT_TXC 0x00800000 309 #define IEVENT_TXE 0x00400000 310 #define IEVENT_TXB 0x00200000 311 #define IEVENT_TXF 0x00100000 312 #define IEVENT_IE 0x00080000 313 #define IEVENT_LC 0x00040000 314 #define IEVENT_CRL 0x00020000 315 #define IEVENT_XFUN 0x00010000 316 #define IEVENT_RXB0 0x00008000 317 #define IEVENT_GRSC 0x00000100 318 #define IEVENT_RXF0 0x00000080 319 320 #define IMASK_INIT_CLEAR 0x00000000 321 #define IMASK_TXEEN 0x00400000 322 #define IMASK_TXBEN 0x00200000 323 #define IMASK_TXFEN 0x00100000 324 #define IMASK_RXFEN0 0x00000080 325 326 327 /* Default Attribute fields */ 328 #define ATTR_INIT_SETTINGS 0x000000c0 329 #define ATTRELI_INIT_SETTINGS 0x00000000 330 331 332 /* TxBD status field bits */ 333 #define TXBD_READY 0x8000 334 #define TXBD_PADCRC 0x4000 335 #define TXBD_WRAP 0x2000 336 #define TXBD_INTERRUPT 0x1000 337 #define TXBD_LAST 0x0800 338 #define TXBD_CRC 0x0400 339 #define TXBD_DEF 0x0200 340 #define TXBD_HUGEFRAME 0x0080 341 #define TXBD_LATECOLLISION 0x0080 342 #define TXBD_RETRYLIMIT 0x0040 343 #define TXBD_RETRYCOUNTMASK 0x003c 344 #define TXBD_UNDERRUN 0x0002 345 #define TXBD_STATS 0x03ff 346 347 /* RxBD status field bits */ 348 #define RXBD_EMPTY 0x8000 349 #define RXBD_RO1 0x4000 350 #define RXBD_WRAP 0x2000 351 #define RXBD_INTERRUPT 0x1000 352 #define RXBD_LAST 0x0800 353 #define RXBD_FIRST 0x0400 354 #define RXBD_MISS 0x0100 355 #define RXBD_BROADCAST 0x0080 356 #define RXBD_MULTICAST 0x0040 357 #define RXBD_LARGE 0x0020 358 #define RXBD_NONOCTET 0x0010 359 #define RXBD_SHORT 0x0008 360 #define RXBD_CRCERR 0x0004 361 #define RXBD_OVERRUN 0x0002 362 #define RXBD_TRUNCATED 0x0001 363 #define RXBD_STATS 0x003f 364 365 typedef struct txbd8 366 { 367 ushort status; /* Status Fields */ 368 ushort length; /* Buffer length */ 369 uint bufPtr; /* Buffer Pointer */ 370 } txbd8_t; 371 372 typedef struct rxbd8 373 { 374 ushort status; /* Status Fields */ 375 ushort length; /* Buffer Length */ 376 uint bufPtr; /* Buffer Pointer */ 377 } rxbd8_t; 378 379 typedef struct rmon_mib 380 { 381 /* Transmit and Receive Counters */ 382 uint tr64; /* Transmit and Receive 64-byte Frame Counter */ 383 uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */ 384 uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */ 385 uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */ 386 uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */ 387 uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */ 388 uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */ 389 /* Receive Counters */ 390 uint rbyt; /* Receive Byte Counter */ 391 uint rpkt; /* Receive Packet Counter */ 392 uint rfcs; /* Receive FCS Error Counter */ 393 uint rmca; /* Receive Multicast Packet (Counter) */ 394 uint rbca; /* Receive Broadcast Packet */ 395 uint rxcf; /* Receive Control Frame Packet */ 396 uint rxpf; /* Receive Pause Frame Packet */ 397 uint rxuo; /* Receive Unknown OP Code */ 398 uint raln; /* Receive Alignment Error */ 399 uint rflr; /* Receive Frame Length Error */ 400 uint rcde; /* Receive Code Error */ 401 uint rcse; /* Receive Carrier Sense Error */ 402 uint rund; /* Receive Undersize Packet */ 403 uint rovr; /* Receive Oversize Packet */ 404 uint rfrg; /* Receive Fragments */ 405 uint rjbr; /* Receive Jabber */ 406 uint rdrp; /* Receive Drop */ 407 /* Transmit Counters */ 408 uint tbyt; /* Transmit Byte Counter */ 409 uint tpkt; /* Transmit Packet */ 410 uint tmca; /* Transmit Multicast Packet */ 411 uint tbca; /* Transmit Broadcast Packet */ 412 uint txpf; /* Transmit Pause Control Frame */ 413 uint tdfr; /* Transmit Deferral Packet */ 414 uint tedf; /* Transmit Excessive Deferral Packet */ 415 uint tscl; /* Transmit Single Collision Packet */ 416 /* (0x2_n700) */ 417 uint tmcl; /* Transmit Multiple Collision Packet */ 418 uint tlcl; /* Transmit Late Collision Packet */ 419 uint txcl; /* Transmit Excessive Collision Packet */ 420 uint tncl; /* Transmit Total Collision */ 421 422 uint res2; 423 424 uint tdrp; /* Transmit Drop Frame */ 425 uint tjbr; /* Transmit Jabber Frame */ 426 uint tfcs; /* Transmit FCS Error */ 427 uint txcf; /* Transmit Control Frame */ 428 uint tovr; /* Transmit Oversize Frame */ 429 uint tund; /* Transmit Undersize Frame */ 430 uint tfrg; /* Transmit Fragments Frame */ 431 /* General Registers */ 432 uint car1; /* Carry Register One */ 433 uint car2; /* Carry Register Two */ 434 uint cam1; /* Carry Register One Mask */ 435 uint cam2; /* Carry Register Two Mask */ 436 } rmon_mib_t; 437 438 typedef struct tsec_hash_regs 439 { 440 uint iaddr0; /* Individual Address Register 0 */ 441 uint iaddr1; /* Individual Address Register 1 */ 442 uint iaddr2; /* Individual Address Register 2 */ 443 uint iaddr3; /* Individual Address Register 3 */ 444 uint iaddr4; /* Individual Address Register 4 */ 445 uint iaddr5; /* Individual Address Register 5 */ 446 uint iaddr6; /* Individual Address Register 6 */ 447 uint iaddr7; /* Individual Address Register 7 */ 448 uint res1[24]; 449 uint gaddr0; /* Group Address Register 0 */ 450 uint gaddr1; /* Group Address Register 1 */ 451 uint gaddr2; /* Group Address Register 2 */ 452 uint gaddr3; /* Group Address Register 3 */ 453 uint gaddr4; /* Group Address Register 4 */ 454 uint gaddr5; /* Group Address Register 5 */ 455 uint gaddr6; /* Group Address Register 6 */ 456 uint gaddr7; /* Group Address Register 7 */ 457 uint res2[24]; 458 } tsec_hash_t; 459 460 typedef struct tsec 461 { 462 /* General Control and Status Registers (0x2_n000) */ 463 uint res000[4]; 464 465 uint ievent; /* Interrupt Event */ 466 uint imask; /* Interrupt Mask */ 467 uint edis; /* Error Disabled */ 468 uint res01c; 469 uint ecntrl; /* Ethernet Control */ 470 uint minflr; /* Minimum Frame Length */ 471 uint ptv; /* Pause Time Value */ 472 uint dmactrl; /* DMA Control */ 473 uint tbipa; /* TBI PHY Address */ 474 475 uint res034[3]; 476 uint res040[48]; 477 478 /* Transmit Control and Status Registers (0x2_n100) */ 479 uint tctrl; /* Transmit Control */ 480 uint tstat; /* Transmit Status */ 481 uint res108; 482 uint tbdlen; /* Tx BD Data Length */ 483 uint res110[5]; 484 uint ctbptr; /* Current TxBD Pointer */ 485 uint res128[23]; 486 uint tbptr; /* TxBD Pointer */ 487 uint res188[30]; 488 /* (0x2_n200) */ 489 uint res200; 490 uint tbase; /* TxBD Base Address */ 491 uint res208[42]; 492 uint ostbd; /* Out of Sequence TxBD */ 493 uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ 494 uint res2b8[18]; 495 496 /* Receive Control and Status Registers (0x2_n300) */ 497 uint rctrl; /* Receive Control */ 498 uint rstat; /* Receive Status */ 499 uint res308; 500 uint rbdlen; /* RxBD Data Length */ 501 uint res310[4]; 502 uint res320; 503 uint crbptr; /* Current Receive Buffer Pointer */ 504 uint res328[6]; 505 uint mrblr; /* Maximum Receive Buffer Length */ 506 uint res344[16]; 507 uint rbptr; /* RxBD Pointer */ 508 uint res388[30]; 509 /* (0x2_n400) */ 510 uint res400; 511 uint rbase; /* RxBD Base Address */ 512 uint res408[62]; 513 514 /* MAC Registers (0x2_n500) */ 515 uint maccfg1; /* MAC Configuration #1 */ 516 uint maccfg2; /* MAC Configuration #2 */ 517 uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */ 518 uint hafdup; /* Half-duplex */ 519 uint maxfrm; /* Maximum Frame */ 520 uint res514; 521 uint res518; 522 523 uint res51c; 524 525 uint miimcfg; /* MII Management: Configuration */ 526 uint miimcom; /* MII Management: Command */ 527 uint miimadd; /* MII Management: Address */ 528 uint miimcon; /* MII Management: Control */ 529 uint miimstat; /* MII Management: Status */ 530 uint miimind; /* MII Management: Indicators */ 531 532 uint res538; 533 534 uint ifstat; /* Interface Status */ 535 uint macstnaddr1; /* Station Address, part 1 */ 536 uint macstnaddr2; /* Station Address, part 2 */ 537 uint res548[46]; 538 539 /* (0x2_n600) */ 540 uint res600[32]; 541 542 /* RMON MIB Registers (0x2_n680-0x2_n73c) */ 543 rmon_mib_t rmon; 544 uint res740[48]; 545 546 /* Hash Function Registers (0x2_n800) */ 547 tsec_hash_t hash; 548 549 uint res900[128]; 550 551 /* Pattern Registers (0x2_nb00) */ 552 uint resb00[62]; 553 uint attr; /* Default Attribute Register */ 554 uint attreli; /* Default Attribute Extract Length and Index */ 555 556 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ 557 uint resc00[256]; 558 } tsec_t; 559 560 #define TSEC_GIGABIT (1) 561 562 /* This flag currently only has 563 * meaning if we're using the eTSEC */ 564 #define TSEC_REDUCED (1 << 1) 565 566 #define TSEC_SGMII (1 << 2) 567 568 struct tsec_private { 569 volatile tsec_t *regs; 570 volatile tsec_t *phyregs; 571 struct phy_info *phyinfo; 572 uint phyaddr; 573 u32 flags; 574 uint link; 575 uint duplexity; 576 uint speed; 577 }; 578 579 580 /* 581 * struct phy_cmd: A command for reading or writing a PHY register 582 * 583 * mii_reg: The register to read or write 584 * 585 * mii_data: For writes, the value to put in the register. 586 * A value of -1 indicates this is a read. 587 * 588 * funct: A function pointer which is invoked for each command. 589 * For reads, this function will be passed the value read 590 * from the PHY, and process it. 591 * For writes, the result of this function will be written 592 * to the PHY register 593 */ 594 struct phy_cmd { 595 uint mii_reg; 596 uint mii_data; 597 uint (*funct) (uint mii_reg, struct tsec_private * priv); 598 }; 599 600 /* struct phy_info: a structure which defines attributes for a PHY 601 * 602 * id will contain a number which represents the PHY. During 603 * startup, the driver will poll the PHY to find out what its 604 * UID--as defined by registers 2 and 3--is. The 32-bit result 605 * gotten from the PHY will be shifted right by "shift" bits to 606 * discard any bits which may change based on revision numbers 607 * unimportant to functionality 608 * 609 * The struct phy_cmd entries represent pointers to an arrays of 610 * commands which tell the driver what to do to the PHY. 611 */ 612 struct phy_info { 613 uint id; 614 char *name; 615 uint shift; 616 /* Called to configure the PHY, and modify the controller 617 * based on the results */ 618 struct phy_cmd *config; 619 620 /* Called when starting up the controller */ 621 struct phy_cmd *startup; 622 623 /* Called when bringing down the controller */ 624 struct phy_cmd *shutdown; 625 }; 626 627 struct tsec_info_struct { 628 tsec_t *regs; 629 tsec_t *miiregs; 630 char *devname; 631 unsigned int phyaddr; 632 u32 flags; 633 }; 634 635 int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info); 636 int tsec_standard_init(bd_t *bis); 637 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num); 638 639 #endif /* __TSEC_H */ 640