1 /* 2 * tsec.h 3 * 4 * Driver for the Motorola Triple Speed Ethernet Controller 5 * 6 * This software may be used and distributed according to the 7 * terms of the GNU Public License, Version 2, incorporated 8 * herein by reference. 9 * 10 * Copyright 2004, 2007 Freescale Semiconductor, Inc. 11 * (C) Copyright 2003, Motorola, Inc. 12 * maintained by Xianghua Xiao (x.xiao@motorola.com) 13 * author Andy Fleming 14 * 15 */ 16 17 #ifndef __TSEC_H 18 #define __TSEC_H 19 20 #include <net.h> 21 #include <config.h> 22 23 #ifndef CONFIG_SYS_TSEC1_OFFSET 24 #define CONFIG_SYS_TSEC1_OFFSET (0x24000) 25 #endif 26 27 #define TSEC_SIZE 0x01000 28 29 /* FIXME: Should these be pushed back to 83xx and 85xx config files? */ 30 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) \ 31 || defined(CONFIG_MPC83xx) 32 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET) 33 #endif 34 35 #define STD_TSEC_INFO(num) \ 36 { \ 37 .regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)), \ 38 .miiregs = (tsec_t *)TSEC_BASE_ADDR, \ 39 .devname = CONFIG_TSEC##num##_NAME, \ 40 .phyaddr = TSEC##num##_PHY_ADDR, \ 41 .flags = TSEC##num##_FLAGS \ 42 } 43 44 #define SET_STD_TSEC_INFO(x, num) \ 45 { \ 46 x.regs = (tsec_t *)(TSEC_BASE_ADDR + ((num - 1) * TSEC_SIZE)); \ 47 x.miiregs = (tsec_t *)TSEC_BASE_ADDR; \ 48 x.devname = CONFIG_TSEC##num##_NAME; \ 49 x.phyaddr = TSEC##num##_PHY_ADDR; \ 50 x.flags = TSEC##num##_FLAGS;\ 51 } 52 53 #define MAC_ADDR_LEN 6 54 55 /* #define TSEC_TIMEOUT 1000000 */ 56 #define TSEC_TIMEOUT 1000 57 #define TOUT_LOOP 1000000 58 59 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */ 60 61 /* TBI register addresses */ 62 #define TBI_CR 0x00 63 #define TBI_SR 0x01 64 #define TBI_ANA 0x04 65 #define TBI_ANLPBPA 0x05 66 #define TBI_ANEX 0x06 67 #define TBI_TBICON 0x11 68 69 /* TBI MDIO register bit fields*/ 70 #define TBICON_CLK_SELECT 0x0020 71 #define TBIANA_ASYMMETRIC_PAUSE 0x0100 72 #define TBIANA_SYMMETRIC_PAUSE 0x0080 73 #define TBIANA_HALF_DUPLEX 0x0040 74 #define TBIANA_FULL_DUPLEX 0x0020 75 #define TBICR_PHY_RESET 0x8000 76 #define TBICR_ANEG_ENABLE 0x1000 77 #define TBICR_RESTART_ANEG 0x0200 78 #define TBICR_FULL_DUPLEX 0x0100 79 #define TBICR_SPEED1_SET 0x0040 80 81 82 /* MAC register bits */ 83 #define MACCFG1_SOFT_RESET 0x80000000 84 #define MACCFG1_RESET_RX_MC 0x00080000 85 #define MACCFG1_RESET_TX_MC 0x00040000 86 #define MACCFG1_RESET_RX_FUN 0x00020000 87 #define MACCFG1_RESET_TX_FUN 0x00010000 88 #define MACCFG1_LOOPBACK 0x00000100 89 #define MACCFG1_RX_FLOW 0x00000020 90 #define MACCFG1_TX_FLOW 0x00000010 91 #define MACCFG1_SYNCD_RX_EN 0x00000008 92 #define MACCFG1_RX_EN 0x00000004 93 #define MACCFG1_SYNCD_TX_EN 0x00000002 94 #define MACCFG1_TX_EN 0x00000001 95 96 #define MACCFG2_INIT_SETTINGS 0x00007205 97 #define MACCFG2_FULL_DUPLEX 0x00000001 98 #define MACCFG2_IF 0x00000300 99 #define MACCFG2_GMII 0x00000200 100 #define MACCFG2_MII 0x00000100 101 102 #define ECNTRL_INIT_SETTINGS 0x00001000 103 #define ECNTRL_TBI_MODE 0x00000020 104 #define ECNTRL_R100 0x00000008 105 #define ECNTRL_SGMII_MODE 0x00000002 106 107 #define miim_end -2 108 #define miim_read -1 109 110 #ifndef CONFIG_SYS_TBIPA_VALUE 111 #define CONFIG_SYS_TBIPA_VALUE 0x1f 112 #endif 113 #define MIIMCFG_INIT_VALUE 0x00000003 114 #define MIIMCFG_RESET 0x80000000 115 116 #define MIIMIND_BUSY 0x00000001 117 #define MIIMIND_NOTVALID 0x00000004 118 119 #define MIIM_CONTROL 0x00 120 #define MIIM_CONTROL_RESET 0x00009140 121 #define MIIM_CONTROL_INIT 0x00001140 122 #define MIIM_CONTROL_RESTART 0x00001340 123 #define MIIM_ANEN 0x00001000 124 125 #define MIIM_CR 0x00 126 #define MIIM_CR_RST 0x00008000 127 #define MIIM_CR_INIT 0x00001000 128 129 #define MIIM_STATUS 0x1 130 #define MIIM_STATUS_AN_DONE 0x00000020 131 #define MIIM_STATUS_LINK 0x0004 132 #define PHY_BMSR_AUTN_ABLE 0x0008 133 #define PHY_BMSR_AUTN_COMP 0x0020 134 135 #define MIIM_PHYIR1 0x2 136 #define MIIM_PHYIR2 0x3 137 138 #define MIIM_ANAR 0x4 139 #define MIIM_ANAR_INIT 0x1e1 140 141 #define MIIM_TBI_ANLPBPA 0x5 142 #define MIIM_TBI_ANLPBPA_HALF 0x00000040 143 #define MIIM_TBI_ANLPBPA_FULL 0x00000020 144 145 #define MIIM_TBI_ANEX 0x6 146 #define MIIM_TBI_ANEX_NP 0x00000004 147 #define MIIM_TBI_ANEX_PRX 0x00000002 148 149 #define MIIM_GBIT_CONTROL 0x9 150 #define MIIM_GBIT_CONTROL_INIT 0xe00 151 152 #define MIIM_EXT_PAGE_ACCESS 0x1f 153 154 /* Broadcom BCM54xx -- taken from linux sungem_phy */ 155 #define MIIM_BCM54xx_AUXCNTL 0x18 156 #define MIIM_BCM54xx_AUXCNTL_ENCODE(val) ((val & 0x7) << 12)|(val & 0x7) 157 #define MIIM_BCM54xx_AUXSTATUS 0x19 158 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700 159 #define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8 160 161 /* Cicada Auxiliary Control/Status Register */ 162 #define MIIM_CIS8201_AUX_CONSTAT 0x1c 163 #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004 164 #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020 165 #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018 166 #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010 167 #define MIIM_CIS8201_AUXCONSTAT_100 0x0008 168 169 /* Cicada Extended Control Register 1 */ 170 #define MIIM_CIS8201_EXT_CON1 0x17 171 #define MIIM_CIS8201_EXTCON1_INIT 0x0000 172 173 /* Cicada 8204 Extended PHY Control Register 1 */ 174 #define MIIM_CIS8204_EPHY_CON 0x17 175 #define MIIM_CIS8204_EPHYCON_INIT 0x0006 176 #define MIIM_CIS8204_EPHYCON_RGMII 0x1100 177 178 /* Cicada 8204 Serial LED Control Register */ 179 #define MIIM_CIS8204_SLED_CON 0x1b 180 #define MIIM_CIS8204_SLEDCON_INIT 0x1115 181 182 #define MIIM_GBIT_CON 0x09 183 #define MIIM_GBIT_CON_ADVERT 0x0e00 184 185 /* Entry for Vitesse VSC8244 regs starts here */ 186 /* Vitesse VSC8244 Auxiliary Control/Status Register */ 187 #define MIIM_VSC8244_AUX_CONSTAT 0x1c 188 #define MIIM_VSC8244_AUXCONSTAT_INIT 0x0000 189 #define MIIM_VSC8244_AUXCONSTAT_DUPLEX 0x0020 190 #define MIIM_VSC8244_AUXCONSTAT_SPEED 0x0018 191 #define MIIM_VSC8244_AUXCONSTAT_GBIT 0x0010 192 #define MIIM_VSC8244_AUXCONSTAT_100 0x0008 193 #define MIIM_CONTROL_INIT_LOOPBACK 0x4000 194 195 /* Vitesse VSC8244 Extended PHY Control Register 1 */ 196 #define MIIM_VSC8244_EPHY_CON 0x17 197 #define MIIM_VSC8244_EPHYCON_INIT 0x0006 198 199 /* Vitesse VSC8244 Serial LED Control Register */ 200 #define MIIM_VSC8244_LED_CON 0x1b 201 #define MIIM_VSC8244_LEDCON_INIT 0xF011 202 203 /* Entry for Vitesse VSC8601 regs starts here (Not complete) */ 204 /* Vitesse VSC8601 Extended PHY Control Register 1 */ 205 #define MIIM_VSC8601_EPHY_CON 0x17 206 #define MIIM_VSC8601_EPHY_CON_INIT_SKEW 0x1120 207 #define MIIM_VSC8601_SKEW_CTRL 0x1c 208 209 /* 88E1011 PHY Status Register */ 210 #define MIIM_88E1011_PHY_STATUS 0x11 211 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000 212 #define MIIM_88E1011_PHYSTAT_GBIT 0x8000 213 #define MIIM_88E1011_PHYSTAT_100 0x4000 214 #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000 215 #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800 216 #define MIIM_88E1011_PHYSTAT_LINK 0x0400 217 218 #define MIIM_88E1011_PHY_SCR 0x10 219 #define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060 220 221 /* 88E1111 PHY LED Control Register */ 222 #define MIIM_88E1111_PHY_LED_CONTROL 24 223 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100 224 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C 225 226 /* 88E1121 PHY LED Control Register */ 227 #define MIIM_88E1121_PHY_LED_CTRL 16 228 #define MIIM_88E1121_PHY_LED_PAGE 3 229 #define MIIM_88E1121_PHY_LED_DEF 0x0030 230 231 /* 88E1121 PHY IRQ Enable/Status Register */ 232 #define MIIM_88E1121_PHY_IRQ_EN 18 233 #define MIIM_88E1121_PHY_IRQ_STATUS 19 234 235 #define MIIM_88E1121_PHY_PAGE 22 236 237 /* 88E1145 Extended PHY Specific Control Register */ 238 #define MIIM_88E1145_PHY_EXT_CR 20 239 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080 240 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002 241 242 #define MIIM_88E1145_PHY_PAGE 29 243 #define MIIM_88E1145_PHY_CAL_OV 30 244 245 /* RTL8211B PHY Status Register */ 246 #define MIIM_RTL8211B_PHY_STATUS 0x11 247 #define MIIM_RTL8211B_PHYSTAT_SPEED 0xc000 248 #define MIIM_RTL8211B_PHYSTAT_GBIT 0x8000 249 #define MIIM_RTL8211B_PHYSTAT_100 0x4000 250 #define MIIM_RTL8211B_PHYSTAT_DUPLEX 0x2000 251 #define MIIM_RTL8211B_PHYSTAT_SPDDONE 0x0800 252 #define MIIM_RTL8211B_PHYSTAT_LINK 0x0400 253 254 /* DM9161 Control register values */ 255 #define MIIM_DM9161_CR_STOP 0x0400 256 #define MIIM_DM9161_CR_RSTAN 0x1200 257 258 #define MIIM_DM9161_SCR 0x10 259 #define MIIM_DM9161_SCR_INIT 0x0610 260 261 /* DM9161 Specified Configuration and Status Register */ 262 #define MIIM_DM9161_SCSR 0x11 263 #define MIIM_DM9161_SCSR_100F 0x8000 264 #define MIIM_DM9161_SCSR_100H 0x4000 265 #define MIIM_DM9161_SCSR_10F 0x2000 266 #define MIIM_DM9161_SCSR_10H 0x1000 267 268 /* DM9161 10BT Configuration/Status */ 269 #define MIIM_DM9161_10BTCSR 0x12 270 #define MIIM_DM9161_10BTCSR_INIT 0x7800 271 272 /* LXT971 Status 2 registers */ 273 #define MIIM_LXT971_SR2 0x11 /* Status Register 2 */ 274 #define MIIM_LXT971_SR2_SPEED_MASK 0x4200 275 #define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */ 276 #define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */ 277 #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */ 278 #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */ 279 280 /* DP83865 Control register values */ 281 #define MIIM_DP83865_CR_INIT 0x9200 282 283 /* DP83865 Link and Auto-Neg Status Register */ 284 #define MIIM_DP83865_LANR 0x11 285 #define MIIM_DP83865_SPD_MASK 0x0018 286 #define MIIM_DP83865_SPD_1000 0x0010 287 #define MIIM_DP83865_SPD_100 0x0008 288 #define MIIM_DP83865_DPX_FULL 0x0002 289 290 #define MIIM_READ_COMMAND 0x00000001 291 292 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN 293 294 #define MINFLR_INIT_SETTINGS 0x00000040 295 296 #define DMACTRL_INIT_SETTINGS 0x000000c3 297 #define DMACTRL_GRS 0x00000010 298 #define DMACTRL_GTS 0x00000008 299 300 #define TSTAT_CLEAR_THALT 0x80000000 301 #define RSTAT_CLEAR_RHALT 0x00800000 302 303 304 #define IEVENT_INIT_CLEAR 0xffffffff 305 #define IEVENT_BABR 0x80000000 306 #define IEVENT_RXC 0x40000000 307 #define IEVENT_BSY 0x20000000 308 #define IEVENT_EBERR 0x10000000 309 #define IEVENT_MSRO 0x04000000 310 #define IEVENT_GTSC 0x02000000 311 #define IEVENT_BABT 0x01000000 312 #define IEVENT_TXC 0x00800000 313 #define IEVENT_TXE 0x00400000 314 #define IEVENT_TXB 0x00200000 315 #define IEVENT_TXF 0x00100000 316 #define IEVENT_IE 0x00080000 317 #define IEVENT_LC 0x00040000 318 #define IEVENT_CRL 0x00020000 319 #define IEVENT_XFUN 0x00010000 320 #define IEVENT_RXB0 0x00008000 321 #define IEVENT_GRSC 0x00000100 322 #define IEVENT_RXF0 0x00000080 323 324 #define IMASK_INIT_CLEAR 0x00000000 325 #define IMASK_TXEEN 0x00400000 326 #define IMASK_TXBEN 0x00200000 327 #define IMASK_TXFEN 0x00100000 328 #define IMASK_RXFEN0 0x00000080 329 330 331 /* Default Attribute fields */ 332 #define ATTR_INIT_SETTINGS 0x000000c0 333 #define ATTRELI_INIT_SETTINGS 0x00000000 334 335 336 /* TxBD status field bits */ 337 #define TXBD_READY 0x8000 338 #define TXBD_PADCRC 0x4000 339 #define TXBD_WRAP 0x2000 340 #define TXBD_INTERRUPT 0x1000 341 #define TXBD_LAST 0x0800 342 #define TXBD_CRC 0x0400 343 #define TXBD_DEF 0x0200 344 #define TXBD_HUGEFRAME 0x0080 345 #define TXBD_LATECOLLISION 0x0080 346 #define TXBD_RETRYLIMIT 0x0040 347 #define TXBD_RETRYCOUNTMASK 0x003c 348 #define TXBD_UNDERRUN 0x0002 349 #define TXBD_STATS 0x03ff 350 351 /* RxBD status field bits */ 352 #define RXBD_EMPTY 0x8000 353 #define RXBD_RO1 0x4000 354 #define RXBD_WRAP 0x2000 355 #define RXBD_INTERRUPT 0x1000 356 #define RXBD_LAST 0x0800 357 #define RXBD_FIRST 0x0400 358 #define RXBD_MISS 0x0100 359 #define RXBD_BROADCAST 0x0080 360 #define RXBD_MULTICAST 0x0040 361 #define RXBD_LARGE 0x0020 362 #define RXBD_NONOCTET 0x0010 363 #define RXBD_SHORT 0x0008 364 #define RXBD_CRCERR 0x0004 365 #define RXBD_OVERRUN 0x0002 366 #define RXBD_TRUNCATED 0x0001 367 #define RXBD_STATS 0x003f 368 369 typedef struct txbd8 370 { 371 ushort status; /* Status Fields */ 372 ushort length; /* Buffer length */ 373 uint bufPtr; /* Buffer Pointer */ 374 } txbd8_t; 375 376 typedef struct rxbd8 377 { 378 ushort status; /* Status Fields */ 379 ushort length; /* Buffer Length */ 380 uint bufPtr; /* Buffer Pointer */ 381 } rxbd8_t; 382 383 typedef struct rmon_mib 384 { 385 /* Transmit and Receive Counters */ 386 uint tr64; /* Transmit and Receive 64-byte Frame Counter */ 387 uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */ 388 uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */ 389 uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */ 390 uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */ 391 uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */ 392 uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */ 393 /* Receive Counters */ 394 uint rbyt; /* Receive Byte Counter */ 395 uint rpkt; /* Receive Packet Counter */ 396 uint rfcs; /* Receive FCS Error Counter */ 397 uint rmca; /* Receive Multicast Packet (Counter) */ 398 uint rbca; /* Receive Broadcast Packet */ 399 uint rxcf; /* Receive Control Frame Packet */ 400 uint rxpf; /* Receive Pause Frame Packet */ 401 uint rxuo; /* Receive Unknown OP Code */ 402 uint raln; /* Receive Alignment Error */ 403 uint rflr; /* Receive Frame Length Error */ 404 uint rcde; /* Receive Code Error */ 405 uint rcse; /* Receive Carrier Sense Error */ 406 uint rund; /* Receive Undersize Packet */ 407 uint rovr; /* Receive Oversize Packet */ 408 uint rfrg; /* Receive Fragments */ 409 uint rjbr; /* Receive Jabber */ 410 uint rdrp; /* Receive Drop */ 411 /* Transmit Counters */ 412 uint tbyt; /* Transmit Byte Counter */ 413 uint tpkt; /* Transmit Packet */ 414 uint tmca; /* Transmit Multicast Packet */ 415 uint tbca; /* Transmit Broadcast Packet */ 416 uint txpf; /* Transmit Pause Control Frame */ 417 uint tdfr; /* Transmit Deferral Packet */ 418 uint tedf; /* Transmit Excessive Deferral Packet */ 419 uint tscl; /* Transmit Single Collision Packet */ 420 /* (0x2_n700) */ 421 uint tmcl; /* Transmit Multiple Collision Packet */ 422 uint tlcl; /* Transmit Late Collision Packet */ 423 uint txcl; /* Transmit Excessive Collision Packet */ 424 uint tncl; /* Transmit Total Collision */ 425 426 uint res2; 427 428 uint tdrp; /* Transmit Drop Frame */ 429 uint tjbr; /* Transmit Jabber Frame */ 430 uint tfcs; /* Transmit FCS Error */ 431 uint txcf; /* Transmit Control Frame */ 432 uint tovr; /* Transmit Oversize Frame */ 433 uint tund; /* Transmit Undersize Frame */ 434 uint tfrg; /* Transmit Fragments Frame */ 435 /* General Registers */ 436 uint car1; /* Carry Register One */ 437 uint car2; /* Carry Register Two */ 438 uint cam1; /* Carry Register One Mask */ 439 uint cam2; /* Carry Register Two Mask */ 440 } rmon_mib_t; 441 442 typedef struct tsec_hash_regs 443 { 444 uint iaddr0; /* Individual Address Register 0 */ 445 uint iaddr1; /* Individual Address Register 1 */ 446 uint iaddr2; /* Individual Address Register 2 */ 447 uint iaddr3; /* Individual Address Register 3 */ 448 uint iaddr4; /* Individual Address Register 4 */ 449 uint iaddr5; /* Individual Address Register 5 */ 450 uint iaddr6; /* Individual Address Register 6 */ 451 uint iaddr7; /* Individual Address Register 7 */ 452 uint res1[24]; 453 uint gaddr0; /* Group Address Register 0 */ 454 uint gaddr1; /* Group Address Register 1 */ 455 uint gaddr2; /* Group Address Register 2 */ 456 uint gaddr3; /* Group Address Register 3 */ 457 uint gaddr4; /* Group Address Register 4 */ 458 uint gaddr5; /* Group Address Register 5 */ 459 uint gaddr6; /* Group Address Register 6 */ 460 uint gaddr7; /* Group Address Register 7 */ 461 uint res2[24]; 462 } tsec_hash_t; 463 464 typedef struct tsec 465 { 466 /* General Control and Status Registers (0x2_n000) */ 467 uint res000[4]; 468 469 uint ievent; /* Interrupt Event */ 470 uint imask; /* Interrupt Mask */ 471 uint edis; /* Error Disabled */ 472 uint res01c; 473 uint ecntrl; /* Ethernet Control */ 474 uint minflr; /* Minimum Frame Length */ 475 uint ptv; /* Pause Time Value */ 476 uint dmactrl; /* DMA Control */ 477 uint tbipa; /* TBI PHY Address */ 478 479 uint res034[3]; 480 uint res040[48]; 481 482 /* Transmit Control and Status Registers (0x2_n100) */ 483 uint tctrl; /* Transmit Control */ 484 uint tstat; /* Transmit Status */ 485 uint res108; 486 uint tbdlen; /* Tx BD Data Length */ 487 uint res110[5]; 488 uint ctbptr; /* Current TxBD Pointer */ 489 uint res128[23]; 490 uint tbptr; /* TxBD Pointer */ 491 uint res188[30]; 492 /* (0x2_n200) */ 493 uint res200; 494 uint tbase; /* TxBD Base Address */ 495 uint res208[42]; 496 uint ostbd; /* Out of Sequence TxBD */ 497 uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */ 498 uint res2b8[18]; 499 500 /* Receive Control and Status Registers (0x2_n300) */ 501 uint rctrl; /* Receive Control */ 502 uint rstat; /* Receive Status */ 503 uint res308; 504 uint rbdlen; /* RxBD Data Length */ 505 uint res310[4]; 506 uint res320; 507 uint crbptr; /* Current Receive Buffer Pointer */ 508 uint res328[6]; 509 uint mrblr; /* Maximum Receive Buffer Length */ 510 uint res344[16]; 511 uint rbptr; /* RxBD Pointer */ 512 uint res388[30]; 513 /* (0x2_n400) */ 514 uint res400; 515 uint rbase; /* RxBD Base Address */ 516 uint res408[62]; 517 518 /* MAC Registers (0x2_n500) */ 519 uint maccfg1; /* MAC Configuration #1 */ 520 uint maccfg2; /* MAC Configuration #2 */ 521 uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */ 522 uint hafdup; /* Half-duplex */ 523 uint maxfrm; /* Maximum Frame */ 524 uint res514; 525 uint res518; 526 527 uint res51c; 528 529 uint miimcfg; /* MII Management: Configuration */ 530 uint miimcom; /* MII Management: Command */ 531 uint miimadd; /* MII Management: Address */ 532 uint miimcon; /* MII Management: Control */ 533 uint miimstat; /* MII Management: Status */ 534 uint miimind; /* MII Management: Indicators */ 535 536 uint res538; 537 538 uint ifstat; /* Interface Status */ 539 uint macstnaddr1; /* Station Address, part 1 */ 540 uint macstnaddr2; /* Station Address, part 2 */ 541 uint res548[46]; 542 543 /* (0x2_n600) */ 544 uint res600[32]; 545 546 /* RMON MIB Registers (0x2_n680-0x2_n73c) */ 547 rmon_mib_t rmon; 548 uint res740[48]; 549 550 /* Hash Function Registers (0x2_n800) */ 551 tsec_hash_t hash; 552 553 uint res900[128]; 554 555 /* Pattern Registers (0x2_nb00) */ 556 uint resb00[62]; 557 uint attr; /* Default Attribute Register */ 558 uint attreli; /* Default Attribute Extract Length and Index */ 559 560 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */ 561 uint resc00[256]; 562 } tsec_t; 563 564 #define TSEC_GIGABIT (1) 565 566 /* This flag currently only has 567 * meaning if we're using the eTSEC */ 568 #define TSEC_REDUCED (1 << 1) 569 570 #define TSEC_SGMII (1 << 2) 571 572 struct tsec_private { 573 volatile tsec_t *regs; 574 volatile tsec_t *phyregs; 575 struct phy_info *phyinfo; 576 uint phyaddr; 577 u32 flags; 578 uint link; 579 uint duplexity; 580 uint speed; 581 }; 582 583 584 /* 585 * struct phy_cmd: A command for reading or writing a PHY register 586 * 587 * mii_reg: The register to read or write 588 * 589 * mii_data: For writes, the value to put in the register. 590 * A value of -1 indicates this is a read. 591 * 592 * funct: A function pointer which is invoked for each command. 593 * For reads, this function will be passed the value read 594 * from the PHY, and process it. 595 * For writes, the result of this function will be written 596 * to the PHY register 597 */ 598 struct phy_cmd { 599 uint mii_reg; 600 uint mii_data; 601 uint (*funct) (uint mii_reg, struct tsec_private * priv); 602 }; 603 604 /* struct phy_info: a structure which defines attributes for a PHY 605 * 606 * id will contain a number which represents the PHY. During 607 * startup, the driver will poll the PHY to find out what its 608 * UID--as defined by registers 2 and 3--is. The 32-bit result 609 * gotten from the PHY will be shifted right by "shift" bits to 610 * discard any bits which may change based on revision numbers 611 * unimportant to functionality 612 * 613 * The struct phy_cmd entries represent pointers to an arrays of 614 * commands which tell the driver what to do to the PHY. 615 */ 616 struct phy_info { 617 uint id; 618 char *name; 619 uint shift; 620 /* Called to configure the PHY, and modify the controller 621 * based on the results */ 622 struct phy_cmd *config; 623 624 /* Called when starting up the controller */ 625 struct phy_cmd *startup; 626 627 /* Called when bringing down the controller */ 628 struct phy_cmd *shutdown; 629 }; 630 631 struct tsec_info_struct { 632 tsec_t *regs; 633 tsec_t *miiregs; 634 char *devname; 635 unsigned int phyaddr; 636 u32 flags; 637 }; 638 639 int tsec_initialize(bd_t * bis, struct tsec_info_struct *tsec_info); 640 int tsec_standard_init(bd_t *bis); 641 int tsec_eth_init(bd_t *bis, struct tsec_info_struct *tsec_info, int num); 642 643 #endif /* __TSEC_H */ 644