1 /* 2 * (C) Copyright 2001 3 * Denis Peter, MPL AG Switzerland 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 * 7 * Most of these definitions are derived from 8 * linux/drivers/scsi/sym53c8xx_defs.h 9 */ 10 11 #ifndef _SYM53C8XX_DEFS_H 12 #define _SYM53C8XX_DEFS_H 13 14 15 #define SCNTL0 0x00 /* full arb., ena parity, par->ATN */ 16 17 #define SCNTL1 0x01 /* no reset */ 18 #define ISCON 0x10 /* connected to scsi */ 19 #define CRST 0x08 /* force reset */ 20 #define IARB 0x02 /* immediate arbitration */ 21 22 #define SCNTL2 0x02 /* no disconnect expected */ 23 #define SDU 0x80 /* cmd: disconnect will raise error */ 24 #define CHM 0x40 /* sta: chained mode */ 25 #define WSS 0x08 /* sta: wide scsi send [W]*/ 26 #define WSR 0x01 /* sta: wide scsi received [W]*/ 27 28 #define SCNTL3 0x03 /* cnf system clock dependent */ 29 #define EWS 0x08 /* cmd: enable wide scsi [W]*/ 30 #define ULTRA 0x80 /* cmd: ULTRA enable */ 31 /* bits 0-2, 7 rsvd for C1010 */ 32 33 #define SCID 0x04 /* cnf host adapter scsi address */ 34 #define RRE 0x40 /* r/w:e enable response to resel. */ 35 #define SRE 0x20 /* r/w:e enable response to select */ 36 37 #define SXFER 0x05 /* ### Sync speed and count */ 38 /* bits 6-7 rsvd for C1010 */ 39 40 #define SDID 0x06 /* ### Destination-ID */ 41 42 #define GPREG 0x07 /* ??? IO-Pins */ 43 44 #define SFBR 0x08 /* ### First byte in phase */ 45 46 #define SOCL 0x09 47 #define CREQ 0x80 /* r/w: SCSI-REQ */ 48 #define CACK 0x40 /* r/w: SCSI-ACK */ 49 #define CBSY 0x20 /* r/w: SCSI-BSY */ 50 #define CSEL 0x10 /* r/w: SCSI-SEL */ 51 #define CATN 0x08 /* r/w: SCSI-ATN */ 52 #define CMSG 0x04 /* r/w: SCSI-MSG */ 53 #define CC_D 0x02 /* r/w: SCSI-C_D */ 54 #define CI_O 0x01 /* r/w: SCSI-I_O */ 55 56 #define SSID 0x0a 57 58 #define SBCL 0x0b 59 60 #define DSTAT 0x0c 61 #define DFE 0x80 /* sta: dma fifo empty */ 62 #define MDPE 0x40 /* int: master data parity error */ 63 #define BF 0x20 /* int: script: bus fault */ 64 #define ABRT 0x10 /* int: script: command aborted */ 65 #define SSI 0x08 /* int: script: single step */ 66 #define SIR 0x04 /* int: script: interrupt instruct. */ 67 #define IID 0x01 /* int: script: illegal instruct. */ 68 69 #define SSTAT0 0x0d 70 #define ILF 0x80 /* sta: data in SIDL register lsb */ 71 #define ORF 0x40 /* sta: data in SODR register lsb */ 72 #define OLF 0x20 /* sta: data in SODL register lsb */ 73 #define AIP 0x10 /* sta: arbitration in progress */ 74 #define LOA 0x08 /* sta: arbitration lost */ 75 #define WOA 0x04 /* sta: arbitration won */ 76 #define IRST 0x02 /* sta: scsi reset signal */ 77 #define SDP 0x01 /* sta: scsi parity signal */ 78 79 #define SSTAT1 0x0e 80 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ 81 82 #define SSTAT2 0x0f 83 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ 84 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ 85 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ 86 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ 87 #define LDSC 0x02 /* sta: disconnect & reconnect */ 88 89 #define DSA 0x10 /* --> Base page */ 90 #define DSA1 0x11 91 #define DSA2 0x12 92 #define DSA3 0x13 93 94 #define ISTAT 0x14 /* --> Main Command and status */ 95 #define CABRT 0x80 /* cmd: abort current operation */ 96 #define SRST 0x40 /* mod: reset chip */ 97 #define SIGP 0x20 /* r/w: message from host to ncr */ 98 #define SEM 0x10 /* r/w: message between host + ncr */ 99 #define CON 0x08 /* sta: connected to scsi */ 100 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ 101 #define SIP 0x02 /* sta: scsi-interrupt */ 102 #define DIP 0x01 /* sta: host/script interrupt */ 103 104 105 #define CTEST0 0x18 106 #define CTEST1 0x19 107 #define CTEST2 0x1a 108 #define CSIGP 0x40 109 /* bits 0-2,7 rsvd for C1010 */ 110 111 #define CTEST3 0x1b 112 #define FLF 0x08 /* cmd: flush dma fifo */ 113 #define CLF 0x04 /* cmd: clear dma fifo */ 114 #define FM 0x02 /* mod: fetch pin mode */ 115 #define WRIE 0x01 /* mod: write and invalidate enable */ 116 /* bits 4-7 rsvd for C1010 */ 117 118 #define DFIFO 0x20 119 #define CTEST4 0x21 120 #define BDIS 0x80 /* mod: burst disable */ 121 #define MPEE 0x08 /* mod: master parity error enable */ 122 123 #define CTEST5 0x22 124 #define DFS 0x20 /* mod: dma fifo size */ 125 /* bits 0-1, 3-7 rsvd for C1010 */ 126 #define CTEST6 0x23 127 128 #define DBC 0x24 /* ### Byte count and command */ 129 #define DNAD 0x28 /* ### Next command register */ 130 #define DSP 0x2c /* --> Script Pointer */ 131 #define DSPS 0x30 /* --> Script pointer save/opcode#2 */ 132 133 #define SCRATCHA 0x34 /* Temporary register a */ 134 #define SCRATCHA1 0x35 135 #define SCRATCHA2 0x36 136 #define SCRATCHA3 0x37 137 138 #define DMODE 0x38 139 #define BL_2 0x80 /* mod: burst length shift value +2 */ 140 #define BL_1 0x40 /* mod: burst length shift value +1 */ 141 #define ERL 0x08 /* mod: enable read line */ 142 #define ERMP 0x04 /* mod: enable read multiple */ 143 #define BOF 0x02 /* mod: burst op code fetch */ 144 #define MAN 0x01 /* mod: manual start */ 145 146 #define DIEN 0x39 147 #define SBR 0x3a 148 149 #define DCNTL 0x3b /* --> Script execution control */ 150 #define CLSE 0x80 /* mod: cache line size enable */ 151 #define PFF 0x40 /* cmd: pre-fetch flush */ 152 #define PFEN 0x20 /* mod: pre-fetch enable */ 153 #define SSM 0x10 /* mod: single step mode */ 154 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ 155 #define STD 0x04 /* cmd: start dma mode */ 156 #define IRQD 0x02 /* mod: irq disable */ 157 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ 158 /* bits 0-1 rsvd for C1010 */ 159 160 #define ADDER 0x3c 161 162 #define SIEN 0x40 /* -->: interrupt enable */ 163 #define SIST 0x42 /* <--: interrupt status */ 164 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ 165 #define STO 0x0400/* sta: timeout (select) */ 166 #define GEN 0x0200/* sta: timeout (general) */ 167 #define HTH 0x0100/* sta: timeout (handshake) */ 168 #define MA 0x80 /* sta: phase mismatch */ 169 #define CMP 0x40 /* sta: arbitration complete */ 170 #define SEL 0x20 /* sta: selected by another device */ 171 #define RSL 0x10 /* sta: reselected by another device*/ 172 #define SGE 0x08 /* sta: gross error (over/underflow)*/ 173 #define UDC 0x04 /* sta: unexpected disconnect */ 174 #define RST 0x02 /* sta: scsi bus reset detected */ 175 #define PAR 0x01 /* sta: scsi parity error */ 176 177 #define SLPAR 0x44 178 #define SWIDE 0x45 179 #define MACNTL 0x46 180 #define GPCNTL 0x47 181 #define STIME0 0x48 /* cmd: timeout for select&handshake*/ 182 #define STIME1 0x49 /* cmd: timeout user defined */ 183 #define RESPID 0x4a /* sta: Reselect-IDs */ 184 185 #define STEST0 0x4c 186 187 #define STEST1 0x4d 188 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ 189 #define DBLEN 0x08 /* clock doubler running */ 190 #define DBLSEL 0x04 /* clock doubler selected */ 191 192 193 #define STEST2 0x4e 194 #define ROF 0x40 /* reset scsi offset (after gross error!) */ 195 #define EXT 0x02 /* extended filtering */ 196 197 #define STEST3 0x4f 198 #define TE 0x80 /* c: tolerAnt enable */ 199 #define HSC 0x20 /* c: Halt SCSI Clock */ 200 #define CSF 0x02 /* c: clear scsi fifo */ 201 202 #define SIDL 0x50 /* Lowlevel: latched from scsi data */ 203 #define STEST4 0x52 204 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ 205 #define SMODE_HVD 0x40 /* High Voltage Differential */ 206 #define SMODE_SE 0x80 /* Single Ended */ 207 #define SMODE_LVD 0xc0 /* Low Voltage Differential */ 208 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ 209 /* bits 0-5 rsvd for C1010 */ 210 211 #define SODL 0x54 /* Lowlevel: data out to scsi data */ 212 213 #define SBDL 0x58 /* Lowlevel: data from scsi data */ 214 215 216 /*----------------------------------------------------------- 217 ** 218 ** Utility macros for the script. 219 ** 220 **----------------------------------------------------------- 221 */ 222 223 #define REG(r) (r) 224 225 /*----------------------------------------------------------- 226 ** 227 ** SCSI phases 228 ** 229 ** DT phases illegal for ncr driver. 230 ** 231 **----------------------------------------------------------- 232 */ 233 234 #define SCR_DATA_OUT 0x00000000 235 #define SCR_DATA_IN 0x01000000 236 #define SCR_COMMAND 0x02000000 237 #define SCR_STATUS 0x03000000 238 #define SCR_DT_DATA_OUT 0x04000000 239 #define SCR_DT_DATA_IN 0x05000000 240 #define SCR_MSG_OUT 0x06000000 241 #define SCR_MSG_IN 0x07000000 242 243 #define SCR_ILG_OUT 0x04000000 244 #define SCR_ILG_IN 0x05000000 245 246 /*----------------------------------------------------------- 247 ** 248 ** Data transfer via SCSI. 249 ** 250 **----------------------------------------------------------- 251 ** 252 ** MOVE_ABS (LEN) 253 ** <<start address>> 254 ** 255 ** MOVE_IND (LEN) 256 ** <<dnad_offset>> 257 ** 258 ** MOVE_TBL 259 ** <<dnad_offset>> 260 ** 261 **----------------------------------------------------------- 262 */ 263 264 #define OPC_MOVE 0x08000000 265 266 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) 267 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) 268 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) 269 270 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) 271 #define SCR_CHMOV_IND(l) ((0x20000000) | (l)) 272 #define SCR_CHMOV_TBL (0x10000000) 273 274 275 /*----------------------------------------------------------- 276 ** 277 ** Selection 278 ** 279 **----------------------------------------------------------- 280 ** 281 ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] 282 ** <<alternate_address>> 283 ** 284 ** SEL_TBL | << dnad_offset>> [ | REL_JMP] 285 ** <<alternate_address>> 286 ** 287 **----------------------------------------------------------- 288 */ 289 290 #define SCR_SEL_ABS 0x40000000 291 #define SCR_SEL_ABS_ATN 0x41000000 292 #define SCR_SEL_TBL 0x42000000 293 #define SCR_SEL_TBL_ATN 0x43000000 294 295 296 #define SCR_JMP_REL 0x04000000 297 #define SCR_ID(id) (((unsigned long)(id)) << 16) 298 299 /*----------------------------------------------------------- 300 ** 301 ** Waiting for Disconnect or Reselect 302 ** 303 **----------------------------------------------------------- 304 ** 305 ** WAIT_DISC 306 ** dummy: <<alternate_address>> 307 ** 308 ** WAIT_RESEL 309 ** <<alternate_address>> 310 ** 311 **----------------------------------------------------------- 312 */ 313 314 #define SCR_WAIT_DISC 0x48000000 315 #define SCR_WAIT_RESEL 0x50000000 316 317 /*----------------------------------------------------------- 318 ** 319 ** Bit Set / Reset 320 ** 321 **----------------------------------------------------------- 322 ** 323 ** SET (flags {|.. }) 324 ** 325 ** CLR (flags {|.. }) 326 ** 327 **----------------------------------------------------------- 328 */ 329 330 #define SCR_SET(f) (0x58000000 | (f)) 331 #define SCR_CLR(f) (0x60000000 | (f)) 332 333 #define SCR_CARRY 0x00000400 334 #define SCR_TRG 0x00000200 335 #define SCR_ACK 0x00000040 336 #define SCR_ATN 0x00000008 337 338 339 /*----------------------------------------------------------- 340 ** 341 ** Memory to memory move 342 ** 343 **----------------------------------------------------------- 344 ** 345 ** COPY (bytecount) 346 ** << source_address >> 347 ** << destination_address >> 348 ** 349 ** SCR_COPY sets the NO FLUSH option by default. 350 ** SCR_COPY_F does not set this option. 351 ** 352 ** For chips which do not support this option, 353 ** ncr_copy_and_bind() will remove this bit. 354 **----------------------------------------------------------- 355 */ 356 357 #define SCR_NO_FLUSH 0x01000000 358 359 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) 360 #define SCR_COPY_F(n) (0xc0000000 | (n)) 361 362 /*----------------------------------------------------------- 363 ** 364 ** Register move and binary operations 365 ** 366 **----------------------------------------------------------- 367 ** 368 ** SFBR_REG (reg, op, data) reg = SFBR op data 369 ** << 0 >> 370 ** 371 ** REG_SFBR (reg, op, data) SFBR = reg op data 372 ** << 0 >> 373 ** 374 ** REG_REG (reg, op, data) reg = reg op data 375 ** << 0 >> 376 ** 377 **----------------------------------------------------------- 378 ** On 810A, 860, 825A, 875, 895 and 896 chips the content 379 ** of SFBR register can be used as data (SCR_SFBR_DATA). 380 ** The 896 has additionnal IO registers starting at 381 ** offset 0x80. Bit 7 of register offset is stored in 382 ** bit 7 of the SCRIPTS instruction first DWORD. 383 **----------------------------------------------------------- 384 */ 385 386 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */ 387 388 #define SCR_SFBR_REG(reg,op,data) \ 389 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 390 391 #define SCR_REG_SFBR(reg,op,data) \ 392 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 393 394 #define SCR_REG_REG(reg,op,data) \ 395 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 396 397 398 #define SCR_LOAD 0x00000000 399 #define SCR_SHL 0x01000000 400 #define SCR_OR 0x02000000 401 #define SCR_XOR 0x03000000 402 #define SCR_AND 0x04000000 403 #define SCR_SHR 0x05000000 404 #define SCR_ADD 0x06000000 405 #define SCR_ADDC 0x07000000 406 407 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ 408 409 /*----------------------------------------------------------- 410 ** 411 ** FROM_REG (reg) SFBR = reg 412 ** << 0 >> 413 ** 414 ** TO_REG (reg) reg = SFBR 415 ** << 0 >> 416 ** 417 ** LOAD_REG (reg, data) reg = <data> 418 ** << 0 >> 419 ** 420 ** LOAD_SFBR(data) SFBR = <data> 421 ** << 0 >> 422 ** 423 **----------------------------------------------------------- 424 */ 425 426 #define SCR_FROM_REG(reg) \ 427 SCR_REG_SFBR(reg,SCR_OR,0) 428 429 #define SCR_TO_REG(reg) \ 430 SCR_SFBR_REG(reg,SCR_OR,0) 431 432 #define SCR_LOAD_REG(reg,data) \ 433 SCR_REG_REG(reg,SCR_LOAD,data) 434 435 #define SCR_LOAD_SFBR(data) \ 436 (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) 437 438 /*----------------------------------------------------------- 439 ** 440 ** LOAD from memory to register. 441 ** STORE from register to memory. 442 ** 443 ** Only supported by 810A, 860, 825A, 875, 895 and 896. 444 ** 445 **----------------------------------------------------------- 446 ** 447 ** LOAD_ABS (LEN) 448 ** <<start address>> 449 ** 450 ** LOAD_REL (LEN) (DSA relative) 451 ** <<dsa_offset>> 452 ** 453 **----------------------------------------------------------- 454 */ 455 456 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) 457 #define SCR_NO_FLUSH2 0x02000000 458 #define SCR_DSA_REL2 0x10000000 459 460 #define SCR_LOAD_R(reg, how, n) \ 461 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) 462 463 #define SCR_STORE_R(reg, how, n) \ 464 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) 465 466 #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) 467 #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) 468 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) 469 #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) 470 471 #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) 472 #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) 473 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) 474 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) 475 476 477 /*----------------------------------------------------------- 478 ** 479 ** Waiting for Disconnect or Reselect 480 ** 481 **----------------------------------------------------------- 482 ** 483 ** JUMP [ | IFTRUE/IFFALSE ( ... ) ] 484 ** <<address>> 485 ** 486 ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] 487 ** <<distance>> 488 ** 489 ** CALL [ | IFTRUE/IFFALSE ( ... ) ] 490 ** <<address>> 491 ** 492 ** CALLR [ | IFTRUE/IFFALSE ( ... ) ] 493 ** <<distance>> 494 ** 495 ** RETURN [ | IFTRUE/IFFALSE ( ... ) ] 496 ** <<dummy>> 497 ** 498 ** INT [ | IFTRUE/IFFALSE ( ... ) ] 499 ** <<ident>> 500 ** 501 ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] 502 ** <<ident>> 503 ** 504 ** Conditions: 505 ** WHEN (phase) 506 ** IF (phase) 507 ** CARRYSET 508 ** DATA (data, mask) 509 ** 510 **----------------------------------------------------------- 511 */ 512 513 #define SCR_NO_OP 0x80000000 514 #define SCR_JUMP 0x80080000 515 #define SCR_JUMP64 0x80480000 516 #define SCR_JUMPR 0x80880000 517 #define SCR_CALL 0x88080000 518 #define SCR_CALLR 0x88880000 519 #define SCR_RETURN 0x90080000 520 #define SCR_INT 0x98080000 521 #define SCR_INT_FLY 0x98180000 522 523 #define IFFALSE(arg) (0x00080000 | (arg)) 524 #define IFTRUE(arg) (0x00000000 | (arg)) 525 526 #define WHEN(phase) (0x00030000 | (phase)) 527 #define IF(phase) (0x00020000 | (phase)) 528 529 #define DATA(D) (0x00040000 | ((D) & 0xff)) 530 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) 531 532 #define CARRYSET (0x00200000) 533 534 535 #define SIR_COMPLETE 0x10000000 536 /* script errors */ 537 #define SIR_SEL_ATN_NO_MSG_OUT 0x00000001 538 #define SIR_CMD_OUT_ILL_PH 0x00000002 539 #define SIR_STATUS_ILL_PH 0x00000003 540 #define SIR_MSG_RECEIVED 0x00000004 541 #define SIR_DATA_IN_ERR 0x00000005 542 #define SIR_DATA_OUT_ERR 0x00000006 543 #define SIR_SCRIPT_ERROR 0x00000007 544 #define SIR_MSG_OUT_NO_CMD 0x00000008 545 #define SIR_MSG_OVER7 0x00000009 546 /* Fly interrupt */ 547 #define INT_ON_FY 0x00000080 548 549 /* Hardware errors are defined in scsi.h */ 550 551 #define SCSI_IDENTIFY 0xC0 552 553 #endif 554