1 /* 2 * (C) Copyright 2001 3 * Denis Peter, MPL AG Switzerland 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 * 24 * Most of these definitions are derived from 25 * linux/drivers/scsi/sym53c8xx_defs.h 26 * 27 */ 28 29 #ifndef _SYM53C8XX_DEFS_H 30 #define _SYM53C8XX_DEFS_H 31 32 33 #define SCNTL0 0x00 /* full arb., ena parity, par->ATN */ 34 35 #define SCNTL1 0x01 /* no reset */ 36 #define ISCON 0x10 /* connected to scsi */ 37 #define CRST 0x08 /* force reset */ 38 #define IARB 0x02 /* immediate arbitration */ 39 40 #define SCNTL2 0x02 /* no disconnect expected */ 41 #define SDU 0x80 /* cmd: disconnect will raise error */ 42 #define CHM 0x40 /* sta: chained mode */ 43 #define WSS 0x08 /* sta: wide scsi send [W]*/ 44 #define WSR 0x01 /* sta: wide scsi received [W]*/ 45 46 #define SCNTL3 0x03 /* cnf system clock dependent */ 47 #define EWS 0x08 /* cmd: enable wide scsi [W]*/ 48 #define ULTRA 0x80 /* cmd: ULTRA enable */ 49 /* bits 0-2, 7 rsvd for C1010 */ 50 51 #define SCID 0x04 /* cnf host adapter scsi address */ 52 #define RRE 0x40 /* r/w:e enable response to resel. */ 53 #define SRE 0x20 /* r/w:e enable response to select */ 54 55 #define SXFER 0x05 /* ### Sync speed and count */ 56 /* bits 6-7 rsvd for C1010 */ 57 58 #define SDID 0x06 /* ### Destination-ID */ 59 60 #define GPREG 0x07 /* ??? IO-Pins */ 61 62 #define SFBR 0x08 /* ### First byte in phase */ 63 64 #define SOCL 0x09 65 #define CREQ 0x80 /* r/w: SCSI-REQ */ 66 #define CACK 0x40 /* r/w: SCSI-ACK */ 67 #define CBSY 0x20 /* r/w: SCSI-BSY */ 68 #define CSEL 0x10 /* r/w: SCSI-SEL */ 69 #define CATN 0x08 /* r/w: SCSI-ATN */ 70 #define CMSG 0x04 /* r/w: SCSI-MSG */ 71 #define CC_D 0x02 /* r/w: SCSI-C_D */ 72 #define CI_O 0x01 /* r/w: SCSI-I_O */ 73 74 #define SSID 0x0a 75 76 #define SBCL 0x0b 77 78 #define DSTAT 0x0c 79 #define DFE 0x80 /* sta: dma fifo empty */ 80 #define MDPE 0x40 /* int: master data parity error */ 81 #define BF 0x20 /* int: script: bus fault */ 82 #define ABRT 0x10 /* int: script: command aborted */ 83 #define SSI 0x08 /* int: script: single step */ 84 #define SIR 0x04 /* int: script: interrupt instruct. */ 85 #define IID 0x01 /* int: script: illegal instruct. */ 86 87 #define SSTAT0 0x0d 88 #define ILF 0x80 /* sta: data in SIDL register lsb */ 89 #define ORF 0x40 /* sta: data in SODR register lsb */ 90 #define OLF 0x20 /* sta: data in SODL register lsb */ 91 #define AIP 0x10 /* sta: arbitration in progress */ 92 #define LOA 0x08 /* sta: arbitration lost */ 93 #define WOA 0x04 /* sta: arbitration won */ 94 #define IRST 0x02 /* sta: scsi reset signal */ 95 #define SDP 0x01 /* sta: scsi parity signal */ 96 97 #define SSTAT1 0x0e 98 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ 99 100 #define SSTAT2 0x0f 101 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ 102 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ 103 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ 104 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ 105 #define LDSC 0x02 /* sta: disconnect & reconnect */ 106 107 #define DSA 0x10 /* --> Base page */ 108 #define DSA1 0x11 109 #define DSA2 0x12 110 #define DSA3 0x13 111 112 #define ISTAT 0x14 /* --> Main Command and status */ 113 #define CABRT 0x80 /* cmd: abort current operation */ 114 #define SRST 0x40 /* mod: reset chip */ 115 #define SIGP 0x20 /* r/w: message from host to ncr */ 116 #define SEM 0x10 /* r/w: message between host + ncr */ 117 #define CON 0x08 /* sta: connected to scsi */ 118 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ 119 #define SIP 0x02 /* sta: scsi-interrupt */ 120 #define DIP 0x01 /* sta: host/script interrupt */ 121 122 123 #define CTEST0 0x18 124 #define CTEST1 0x19 125 #define CTEST2 0x1a 126 #define CSIGP 0x40 127 /* bits 0-2,7 rsvd for C1010 */ 128 129 #define CTEST3 0x1b 130 #define FLF 0x08 /* cmd: flush dma fifo */ 131 #define CLF 0x04 /* cmd: clear dma fifo */ 132 #define FM 0x02 /* mod: fetch pin mode */ 133 #define WRIE 0x01 /* mod: write and invalidate enable */ 134 /* bits 4-7 rsvd for C1010 */ 135 136 #define DFIFO 0x20 137 #define CTEST4 0x21 138 #define BDIS 0x80 /* mod: burst disable */ 139 #define MPEE 0x08 /* mod: master parity error enable */ 140 141 #define CTEST5 0x22 142 #define DFS 0x20 /* mod: dma fifo size */ 143 /* bits 0-1, 3-7 rsvd for C1010 */ 144 #define CTEST6 0x23 145 146 #define DBC 0x24 /* ### Byte count and command */ 147 #define DNAD 0x28 /* ### Next command register */ 148 #define DSP 0x2c /* --> Script Pointer */ 149 #define DSPS 0x30 /* --> Script pointer save/opcode#2 */ 150 151 #define SCRATCHA 0x34 /* Temporary register a */ 152 #define SCRATCHA1 0x35 153 #define SCRATCHA2 0x36 154 #define SCRATCHA3 0x37 155 156 #define DMODE 0x38 157 #define BL_2 0x80 /* mod: burst length shift value +2 */ 158 #define BL_1 0x40 /* mod: burst length shift value +1 */ 159 #define ERL 0x08 /* mod: enable read line */ 160 #define ERMP 0x04 /* mod: enable read multiple */ 161 #define BOF 0x02 /* mod: burst op code fetch */ 162 #define MAN 0x01 /* mod: manual start */ 163 164 #define DIEN 0x39 165 #define SBR 0x3a 166 167 #define DCNTL 0x3b /* --> Script execution control */ 168 #define CLSE 0x80 /* mod: cache line size enable */ 169 #define PFF 0x40 /* cmd: pre-fetch flush */ 170 #define PFEN 0x20 /* mod: pre-fetch enable */ 171 #define SSM 0x10 /* mod: single step mode */ 172 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ 173 #define STD 0x04 /* cmd: start dma mode */ 174 #define IRQD 0x02 /* mod: irq disable */ 175 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ 176 /* bits 0-1 rsvd for C1010 */ 177 178 #define ADDER 0x3c 179 180 #define SIEN 0x40 /* -->: interrupt enable */ 181 #define SIST 0x42 /* <--: interrupt status */ 182 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ 183 #define STO 0x0400/* sta: timeout (select) */ 184 #define GEN 0x0200/* sta: timeout (general) */ 185 #define HTH 0x0100/* sta: timeout (handshake) */ 186 #define MA 0x80 /* sta: phase mismatch */ 187 #define CMP 0x40 /* sta: arbitration complete */ 188 #define SEL 0x20 /* sta: selected by another device */ 189 #define RSL 0x10 /* sta: reselected by another device*/ 190 #define SGE 0x08 /* sta: gross error (over/underflow)*/ 191 #define UDC 0x04 /* sta: unexpected disconnect */ 192 #define RST 0x02 /* sta: scsi bus reset detected */ 193 #define PAR 0x01 /* sta: scsi parity error */ 194 195 #define SLPAR 0x44 196 #define SWIDE 0x45 197 #define MACNTL 0x46 198 #define GPCNTL 0x47 199 #define STIME0 0x48 /* cmd: timeout for select&handshake*/ 200 #define STIME1 0x49 /* cmd: timeout user defined */ 201 #define RESPID 0x4a /* sta: Reselect-IDs */ 202 203 #define STEST0 0x4c 204 205 #define STEST1 0x4d 206 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ 207 #define DBLEN 0x08 /* clock doubler running */ 208 #define DBLSEL 0x04 /* clock doubler selected */ 209 210 211 #define STEST2 0x4e 212 #define ROF 0x40 /* reset scsi offset (after gross error!) */ 213 #define EXT 0x02 /* extended filtering */ 214 215 #define STEST3 0x4f 216 #define TE 0x80 /* c: tolerAnt enable */ 217 #define HSC 0x20 /* c: Halt SCSI Clock */ 218 #define CSF 0x02 /* c: clear scsi fifo */ 219 220 #define SIDL 0x50 /* Lowlevel: latched from scsi data */ 221 #define STEST4 0x52 222 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ 223 #define SMODE_HVD 0x40 /* High Voltage Differential */ 224 #define SMODE_SE 0x80 /* Single Ended */ 225 #define SMODE_LVD 0xc0 /* Low Voltage Differential */ 226 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ 227 /* bits 0-5 rsvd for C1010 */ 228 229 #define SODL 0x54 /* Lowlevel: data out to scsi data */ 230 231 #define SBDL 0x58 /* Lowlevel: data from scsi data */ 232 233 234 235 236 /*----------------------------------------------------------- 237 ** 238 ** Utility macros for the script. 239 ** 240 **----------------------------------------------------------- 241 */ 242 243 #define REG(r) (r) 244 245 /*----------------------------------------------------------- 246 ** 247 ** SCSI phases 248 ** 249 ** DT phases illegal for ncr driver. 250 ** 251 **----------------------------------------------------------- 252 */ 253 254 #define SCR_DATA_OUT 0x00000000 255 #define SCR_DATA_IN 0x01000000 256 #define SCR_COMMAND 0x02000000 257 #define SCR_STATUS 0x03000000 258 #define SCR_DT_DATA_OUT 0x04000000 259 #define SCR_DT_DATA_IN 0x05000000 260 #define SCR_MSG_OUT 0x06000000 261 #define SCR_MSG_IN 0x07000000 262 263 #define SCR_ILG_OUT 0x04000000 264 #define SCR_ILG_IN 0x05000000 265 266 /*----------------------------------------------------------- 267 ** 268 ** Data transfer via SCSI. 269 ** 270 **----------------------------------------------------------- 271 ** 272 ** MOVE_ABS (LEN) 273 ** <<start address>> 274 ** 275 ** MOVE_IND (LEN) 276 ** <<dnad_offset>> 277 ** 278 ** MOVE_TBL 279 ** <<dnad_offset>> 280 ** 281 **----------------------------------------------------------- 282 */ 283 284 #define OPC_MOVE 0x08000000 285 286 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) 287 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) 288 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) 289 290 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) 291 #define SCR_CHMOV_IND(l) ((0x20000000) | (l)) 292 #define SCR_CHMOV_TBL (0x10000000) 293 294 295 /*----------------------------------------------------------- 296 ** 297 ** Selection 298 ** 299 **----------------------------------------------------------- 300 ** 301 ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] 302 ** <<alternate_address>> 303 ** 304 ** SEL_TBL | << dnad_offset>> [ | REL_JMP] 305 ** <<alternate_address>> 306 ** 307 **----------------------------------------------------------- 308 */ 309 310 #define SCR_SEL_ABS 0x40000000 311 #define SCR_SEL_ABS_ATN 0x41000000 312 #define SCR_SEL_TBL 0x42000000 313 #define SCR_SEL_TBL_ATN 0x43000000 314 315 316 #define SCR_JMP_REL 0x04000000 317 #define SCR_ID(id) (((unsigned long)(id)) << 16) 318 319 /*----------------------------------------------------------- 320 ** 321 ** Waiting for Disconnect or Reselect 322 ** 323 **----------------------------------------------------------- 324 ** 325 ** WAIT_DISC 326 ** dummy: <<alternate_address>> 327 ** 328 ** WAIT_RESEL 329 ** <<alternate_address>> 330 ** 331 **----------------------------------------------------------- 332 */ 333 334 #define SCR_WAIT_DISC 0x48000000 335 #define SCR_WAIT_RESEL 0x50000000 336 337 /*----------------------------------------------------------- 338 ** 339 ** Bit Set / Reset 340 ** 341 **----------------------------------------------------------- 342 ** 343 ** SET (flags {|.. }) 344 ** 345 ** CLR (flags {|.. }) 346 ** 347 **----------------------------------------------------------- 348 */ 349 350 #define SCR_SET(f) (0x58000000 | (f)) 351 #define SCR_CLR(f) (0x60000000 | (f)) 352 353 #define SCR_CARRY 0x00000400 354 #define SCR_TRG 0x00000200 355 #define SCR_ACK 0x00000040 356 #define SCR_ATN 0x00000008 357 358 359 360 361 /*----------------------------------------------------------- 362 ** 363 ** Memory to memory move 364 ** 365 **----------------------------------------------------------- 366 ** 367 ** COPY (bytecount) 368 ** << source_address >> 369 ** << destination_address >> 370 ** 371 ** SCR_COPY sets the NO FLUSH option by default. 372 ** SCR_COPY_F does not set this option. 373 ** 374 ** For chips which do not support this option, 375 ** ncr_copy_and_bind() will remove this bit. 376 **----------------------------------------------------------- 377 */ 378 379 #define SCR_NO_FLUSH 0x01000000 380 381 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) 382 #define SCR_COPY_F(n) (0xc0000000 | (n)) 383 384 /*----------------------------------------------------------- 385 ** 386 ** Register move and binary operations 387 ** 388 **----------------------------------------------------------- 389 ** 390 ** SFBR_REG (reg, op, data) reg = SFBR op data 391 ** << 0 >> 392 ** 393 ** REG_SFBR (reg, op, data) SFBR = reg op data 394 ** << 0 >> 395 ** 396 ** REG_REG (reg, op, data) reg = reg op data 397 ** << 0 >> 398 ** 399 **----------------------------------------------------------- 400 ** On 810A, 860, 825A, 875, 895 and 896 chips the content 401 ** of SFBR register can be used as data (SCR_SFBR_DATA). 402 ** The 896 has additionnal IO registers starting at 403 ** offset 0x80. Bit 7 of register offset is stored in 404 ** bit 7 of the SCRIPTS instruction first DWORD. 405 **----------------------------------------------------------- 406 */ 407 408 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */ 409 410 #define SCR_SFBR_REG(reg,op,data) \ 411 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 412 413 #define SCR_REG_SFBR(reg,op,data) \ 414 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 415 416 #define SCR_REG_REG(reg,op,data) \ 417 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) 418 419 420 #define SCR_LOAD 0x00000000 421 #define SCR_SHL 0x01000000 422 #define SCR_OR 0x02000000 423 #define SCR_XOR 0x03000000 424 #define SCR_AND 0x04000000 425 #define SCR_SHR 0x05000000 426 #define SCR_ADD 0x06000000 427 #define SCR_ADDC 0x07000000 428 429 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ 430 431 /*----------------------------------------------------------- 432 ** 433 ** FROM_REG (reg) SFBR = reg 434 ** << 0 >> 435 ** 436 ** TO_REG (reg) reg = SFBR 437 ** << 0 >> 438 ** 439 ** LOAD_REG (reg, data) reg = <data> 440 ** << 0 >> 441 ** 442 ** LOAD_SFBR(data) SFBR = <data> 443 ** << 0 >> 444 ** 445 **----------------------------------------------------------- 446 */ 447 448 #define SCR_FROM_REG(reg) \ 449 SCR_REG_SFBR(reg,SCR_OR,0) 450 451 #define SCR_TO_REG(reg) \ 452 SCR_SFBR_REG(reg,SCR_OR,0) 453 454 #define SCR_LOAD_REG(reg,data) \ 455 SCR_REG_REG(reg,SCR_LOAD,data) 456 457 #define SCR_LOAD_SFBR(data) \ 458 (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) 459 460 /*----------------------------------------------------------- 461 ** 462 ** LOAD from memory to register. 463 ** STORE from register to memory. 464 ** 465 ** Only supported by 810A, 860, 825A, 875, 895 and 896. 466 ** 467 **----------------------------------------------------------- 468 ** 469 ** LOAD_ABS (LEN) 470 ** <<start address>> 471 ** 472 ** LOAD_REL (LEN) (DSA relative) 473 ** <<dsa_offset>> 474 ** 475 **----------------------------------------------------------- 476 */ 477 478 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) 479 #define SCR_NO_FLUSH2 0x02000000 480 #define SCR_DSA_REL2 0x10000000 481 482 #define SCR_LOAD_R(reg, how, n) \ 483 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) 484 485 #define SCR_STORE_R(reg, how, n) \ 486 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) 487 488 #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) 489 #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) 490 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) 491 #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) 492 493 #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) 494 #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) 495 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) 496 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) 497 498 499 /*----------------------------------------------------------- 500 ** 501 ** Waiting for Disconnect or Reselect 502 ** 503 **----------------------------------------------------------- 504 ** 505 ** JUMP [ | IFTRUE/IFFALSE ( ... ) ] 506 ** <<address>> 507 ** 508 ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] 509 ** <<distance>> 510 ** 511 ** CALL [ | IFTRUE/IFFALSE ( ... ) ] 512 ** <<address>> 513 ** 514 ** CALLR [ | IFTRUE/IFFALSE ( ... ) ] 515 ** <<distance>> 516 ** 517 ** RETURN [ | IFTRUE/IFFALSE ( ... ) ] 518 ** <<dummy>> 519 ** 520 ** INT [ | IFTRUE/IFFALSE ( ... ) ] 521 ** <<ident>> 522 ** 523 ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] 524 ** <<ident>> 525 ** 526 ** Conditions: 527 ** WHEN (phase) 528 ** IF (phase) 529 ** CARRYSET 530 ** DATA (data, mask) 531 ** 532 **----------------------------------------------------------- 533 */ 534 535 #define SCR_NO_OP 0x80000000 536 #define SCR_JUMP 0x80080000 537 #define SCR_JUMP64 0x80480000 538 #define SCR_JUMPR 0x80880000 539 #define SCR_CALL 0x88080000 540 #define SCR_CALLR 0x88880000 541 #define SCR_RETURN 0x90080000 542 #define SCR_INT 0x98080000 543 #define SCR_INT_FLY 0x98180000 544 545 #define IFFALSE(arg) (0x00080000 | (arg)) 546 #define IFTRUE(arg) (0x00000000 | (arg)) 547 548 #define WHEN(phase) (0x00030000 | (phase)) 549 #define IF(phase) (0x00020000 | (phase)) 550 551 #define DATA(D) (0x00040000 | ((D) & 0xff)) 552 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) 553 554 #define CARRYSET (0x00200000) 555 556 557 558 #define SIR_COMPLETE 0x10000000 559 /* script errors */ 560 #define SIR_SEL_ATN_NO_MSG_OUT 0x00000001 561 #define SIR_CMD_OUT_ILL_PH 0x00000002 562 #define SIR_STATUS_ILL_PH 0x00000003 563 #define SIR_MSG_RECEIVED 0x00000004 564 #define SIR_DATA_IN_ERR 0x00000005 565 #define SIR_DATA_OUT_ERR 0x00000006 566 #define SIR_SCRIPT_ERROR 0x00000007 567 #define SIR_MSG_OUT_NO_CMD 0x00000008 568 #define SIR_MSG_OVER7 0x00000009 569 /* Fly interrupt */ 570 #define INT_ON_FY 0x00000080 571 572 /* Hardware errors are defined in scsi.h */ 573 574 #define SCSI_IDENTIFY 0xC0 575 576 #ifndef TRUE 577 #define TRUE 1 578 #endif 579 #ifndef FALSE 580 #define FALSE 0 581 #endif 582 583 #endif 584