1 /* 2 * (C) Copyright 2002 3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #ifndef _SPARTAN3_H_ 9 #define _SPARTAN3_H_ 10 11 #include <xilinx.h> 12 13 extern int Spartan3_load(Xilinx_desc *desc, const void *image, size_t size); 14 extern int Spartan3_dump(Xilinx_desc *desc, const void *buf, size_t bsize); 15 extern int Spartan3_info(Xilinx_desc *desc); 16 17 /* Slave Parallel Implementation function table */ 18 typedef struct { 19 Xilinx_pre_fn pre; 20 Xilinx_pgm_fn pgm; 21 Xilinx_init_fn init; 22 Xilinx_err_fn err; 23 Xilinx_done_fn done; 24 Xilinx_clk_fn clk; 25 Xilinx_cs_fn cs; 26 Xilinx_wr_fn wr; 27 Xilinx_rdata_fn rdata; 28 Xilinx_wdata_fn wdata; 29 Xilinx_busy_fn busy; 30 Xilinx_abort_fn abort; 31 Xilinx_post_fn post; 32 } Xilinx_Spartan3_Slave_Parallel_fns; 33 34 /* Slave Serial Implementation function table */ 35 typedef struct { 36 Xilinx_pre_fn pre; 37 Xilinx_pgm_fn pgm; 38 Xilinx_clk_fn clk; 39 Xilinx_init_fn init; 40 Xilinx_done_fn done; 41 Xilinx_wr_fn wr; 42 Xilinx_post_fn post; 43 Xilinx_bwr_fn bwr; /* block write function */ 44 Xilinx_abort_fn abort; 45 } Xilinx_Spartan3_Slave_Serial_fns; 46 47 /* Device Image Sizes 48 *********************************************************************/ 49 /* Spartan-III (1.2V) */ 50 #define XILINX_XC3S50_SIZE 439264/8 51 #define XILINX_XC3S200_SIZE 1047616/8 52 #define XILINX_XC3S400_SIZE 1699136/8 53 #define XILINX_XC3S1000_SIZE 3223488/8 54 #define XILINX_XC3S1500_SIZE 5214784/8 55 #define XILINX_XC3S2000_SIZE 7673024/8 56 #define XILINX_XC3S4000_SIZE 11316864/8 57 #define XILINX_XC3S5000_SIZE 13271936/8 58 59 /* Spartan-3E (v3.4) */ 60 #define XILINX_XC3S100E_SIZE 581344/8 61 #define XILINX_XC3S250E_SIZE 1353728/8 62 #define XILINX_XC3S500E_SIZE 2270208/8 63 #define XILINX_XC3S1200E_SIZE 3841184/8 64 #define XILINX_XC3S1600E_SIZE 5969696/8 65 66 /* 67 * Spartan-6 : the Spartan-6 family can be programmed 68 * exactly as the Spartan-3 69 */ 70 #define XILINK_XC6SLX4_SIZE (3713568/8) 71 72 /* Descriptor Macros 73 *********************************************************************/ 74 /* Spartan-III devices */ 75 #define XILINX_XC3S50_DESC(iface, fn_table, cookie) \ 76 { Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie } 77 78 #define XILINX_XC3S200_DESC(iface, fn_table, cookie) \ 79 { Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie } 80 81 #define XILINX_XC3S400_DESC(iface, fn_table, cookie) \ 82 { Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie } 83 84 #define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \ 85 { Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie } 86 87 #define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \ 88 { Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie } 89 90 #define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \ 91 { Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie } 92 93 #define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \ 94 { Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie } 95 96 #define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \ 97 { Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie } 98 99 /* Spartan-3E devices */ 100 #define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \ 101 { Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie } 102 103 #define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \ 104 { Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie } 105 106 #define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \ 107 { Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie } 108 109 #define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \ 110 { Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie } 111 112 #define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \ 113 { Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie } 114 115 #define XILINX_XC6SLX4_DESC(iface, fn_table, cookie) \ 116 { Xilinx_Spartan3, iface, XILINK_XC6SLX4_SIZE, fn_table, cookie } 117 118 #endif /* _SPARTAN3_H_ */ 119