1/* 2 * (C) Copyright 2000-2002 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * This file contains all the macros and symbols which define 10 * a PowerPC assembly language environment. 11 */ 12#ifndef __PPC_ASM_TMPL__ 13#define __PPC_ASM_TMPL__ 14 15/*************************************************************************** 16 * 17 * These definitions simplify the ugly declarations necessary for GOT 18 * definitions. 19 * 20 * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es 21 * 22 * Uses r12 to access the GOT 23 */ 24 25#define START_GOT \ 26 .section ".got2","aw"; \ 27.LCTOC1 = .+32768 28 29#define END_GOT \ 30 .text 31 32#define GET_GOT \ 33 bl 1f ; \ 34 .text 2 ; \ 350: .long .LCTOC1-1f ; \ 36 .text ; \ 371: mflr r12 ; \ 38 lwz r0,0b-1b(r12) ; \ 39 add r12,r0,r12 ; 40 41#define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME 42 43#define GOT(NAME) .L_ ## NAME (r12) 44 45 46/*************************************************************************** 47 * Register names 48 */ 49#define r0 0 50#define r1 1 51#define r2 2 52#define r3 3 53#define r4 4 54#define r5 5 55#define r6 6 56#define r7 7 57#define r8 8 58#define r9 9 59#define r10 10 60#define r11 11 61#define r12 12 62#define r13 13 63#define r14 14 64#define r15 15 65#define r16 16 66#define r17 17 67#define r18 18 68#define r19 19 69#define r20 20 70#define r21 21 71#define r22 22 72#define r23 23 73#define r24 24 74#define r25 25 75#define r26 26 76#define r27 27 77#define r28 28 78#define r29 29 79#define r30 30 80#define r31 31 81 82 83#if defined(CONFIG_8xx) 84 85/* Some special registers */ 86 87#define ICR 148 /* Interrupt Cause Register (37-44) */ 88#define DER 149 89#define COUNTA 150 /* Breakpoint Counter (37-44) */ 90#define COUNTB 151 /* Breakpoint Counter (37-44) */ 91#define LCTRL1 156 /* Load/Store Support (37-40) */ 92#define LCTRL2 157 /* Load/Store Support (37-41) */ 93#define ICTRL 158 94 95#endif /* CONFIG_8xx */ 96 97 98#if defined(CONFIG_5xx) 99/* Some special purpose registers */ 100#define DER 149 /* Debug Enable Register */ 101#define COUNTA 150 /* Breakpoint Counter */ 102#define COUNTB 151 /* Breakpoint Counter */ 103#define LCTRL1 156 /* Load/Store Support */ 104#define LCTRL2 157 /* Load/Store Support */ 105#define ICTRL 158 /* I-Bus Support Control Register */ 106#define EID 81 107#endif /* CONFIG_5xx */ 108 109#if defined(CONFIG_8xx) 110 111/* Registers in the processor's internal memory map that we use. 112*/ 113#define SYPCR 0x00000004 114#define BR0 0x00000100 115#define OR0 0x00000104 116#define BR1 0x00000108 117#define OR1 0x0000010c 118#define BR2 0x00000110 119#define OR2 0x00000114 120#define BR3 0x00000118 121#define OR3 0x0000011c 122#define BR4 0x00000120 123#define OR4 0x00000124 124 125#define MAR 0x00000164 126#define MCR 0x00000168 127#define MAMR 0x00000170 128#define MBMR 0x00000174 129#define MSTAT 0x00000178 130#define MPTPR 0x0000017a 131#define MDR 0x0000017c 132 133#define TBSCR 0x00000200 134#define TBREFF0 0x00000204 135 136#define PLPRCR 0x00000284 137 138#elif defined(CONFIG_MPC8260) 139 140#define HID2 1011 141 142#define HID0_IFEM (1<<7) 143 144#define HID0_ICE_BITPOS 16 145#define HID0_DCE_BITPOS 17 146 147#define IM_REGBASE 0x10000 148#define IM_SYPCR (IM_REGBASE+0x0004) 149#define IM_SWSR (IM_REGBASE+0x000e) 150#define IM_BR0 (IM_REGBASE+0x0100) 151#define IM_OR0 (IM_REGBASE+0x0104) 152#define IM_BR1 (IM_REGBASE+0x0108) 153#define IM_OR1 (IM_REGBASE+0x010c) 154#define IM_BR2 (IM_REGBASE+0x0110) 155#define IM_OR2 (IM_REGBASE+0x0114) 156#define IM_MPTPR (IM_REGBASE+0x0184) 157#define IM_PSDMR (IM_REGBASE+0x0190) 158#define IM_PSRT (IM_REGBASE+0x019c) 159#define IM_IMMR (IM_REGBASE+0x01a8) 160#define IM_SCCR (IM_REGBASE+0x0c80) 161 162#elif defined(CONFIG_MPC5xxx) 163 164#define HID0_ICE_BITPOS 16 165#define HID0_DCE_BITPOS 17 166 167#endif 168 169#define curptr r2 170 171#define SYNC \ 172 sync; \ 173 isync 174 175/* 176 * Macros for storing registers into and loading registers from 177 * exception frames. 178 */ 179#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 180#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 181#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 182#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 183#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 184#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 185#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 186#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 187#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 188#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 189 190/* 191 * GCC sometimes accesses words at negative offsets from the stack 192 * pointer, although the SysV ABI says it shouldn't. To cope with 193 * this, we leave this much untouched space on the stack on exception 194 * entry. 195 */ 196#define STACK_UNDERHEAD 64 197 198/* 199 * Exception entry code. This code runs with address translation 200 * turned off, i.e. using physical addresses. 201 * We assume sprg3 has the physical address of the current 202 * task's thread_struct. 203 */ 204#define EXCEPTION_PROLOG(reg1, reg2) \ 205 mtspr SPRG0,r20; \ 206 mtspr SPRG1,r21; \ 207 mfcr r20; \ 208 subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\ 209 stw r20,_CCR(r21); /* save registers */ \ 210 stw r22,GPR22(r21); \ 211 stw r23,GPR23(r21); \ 212 mfspr r20,SPRG0; \ 213 stw r20,GPR20(r21); \ 214 mfspr r22,SPRG1; \ 215 stw r22,GPR21(r21); \ 216 mflr r20; \ 217 stw r20,_LINK(r21); \ 218 mfctr r22; \ 219 stw r22,_CTR(r21); \ 220 mfspr r20,XER; \ 221 stw r20,_XER(r21); \ 222 mfspr r20, DAR_DEAR; \ 223 stw r20,_DAR(r21); \ 224 mfspr r22,reg1; \ 225 mfspr r23,reg2; \ 226 stw r0,GPR0(r21); \ 227 stw r1,GPR1(r21); \ 228 stw r2,GPR2(r21); \ 229 stw r1,0(r21); \ 230 mr r1,r21; /* set new kernel sp */ \ 231 SAVE_4GPRS(3, r21); 232/* 233 * Note: code which follows this uses cr0.eq (set if from kernel), 234 * r21, r22 (SRR0), and r23 (SRR1). 235 */ 236 237/* 238 * Exception vectors. 239 * 240 * The data words for `hdlr' and `int_return' are initialized with 241 * OFFSET values only; they must be relocated first before they can 242 * be used! 243 */ 244#define COPY_EE(d, s) rlwimi d,s,0,16,16 245#define NOCOPY(d, s) 246#define EXC_XFER_TEMPLATE(label, hdlr, msr, copyee) \ 247 bl 1f; \ 2481: mflr r20; \ 249 lwz r20,(.L_ ## label)-1b+8(r20); \ 250 mtlr r20; \ 251 li r20,msr; \ 252 copyee(r20,r23); \ 253 rlwimi r20,r23,0,25,25; \ 254 blrl; \ 255.L_ ## label : \ 256 .long hdlr - _start + _START_OFFSET; \ 257 .long int_return - _start + _START_OFFSET; \ 258 .long transfer_to_handler - _start + _START_OFFSET 259 260#define STD_EXCEPTION(n, label, hdlr) \ 261 . = n; \ 262label: \ 263 EXCEPTION_PROLOG(SRR0, SRR1); \ 264 addi r3,r1,STACK_FRAME_OVERHEAD; \ 265 EXC_XFER_TEMPLATE(label, hdlr, MSR_KERNEL, NOCOPY) \ 266 267#define CRIT_EXCEPTION(n, label, hdlr) \ 268 . = n; \ 269label: \ 270 EXCEPTION_PROLOG(CSRR0, CSRR1); \ 271 addi r3,r1,STACK_FRAME_OVERHEAD; \ 272 EXC_XFER_TEMPLATE(label, hdlr, \ 273 MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \ 274 275#define MCK_EXCEPTION(n, label, hdlr) \ 276 . = n; \ 277label: \ 278 EXCEPTION_PROLOG(MCSRR0, MCSRR1); \ 279 addi r3,r1,STACK_FRAME_OVERHEAD; \ 280 EXC_XFER_TEMPLATE(label, hdlr, \ 281 MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \ 282 283#endif /* __PPC_ASM_TMPL__ */ 284