1d62589d5Swdenk/* 2d62589d5Swdenk * (C) Copyright 2000-2002 3d62589d5Swdenk * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4d62589d5Swdenk * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6d62589d5Swdenk */ 7d62589d5Swdenk 8d62589d5Swdenk/* 9d62589d5Swdenk * This file contains all the macros and symbols which define 10d62589d5Swdenk * a PowerPC assembly language environment. 11d62589d5Swdenk */ 12d62589d5Swdenk#ifndef __PPC_ASM_TMPL__ 13d62589d5Swdenk#define __PPC_ASM_TMPL__ 14d62589d5Swdenk 15d62589d5Swdenk/*************************************************************************** 16d62589d5Swdenk * 17d62589d5Swdenk * These definitions simplify the ugly declarations necessary for GOT 18d62589d5Swdenk * definitions. 19d62589d5Swdenk * 20d62589d5Swdenk * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es 21d62589d5Swdenk * 22161e4ae4SHeiko Schocher * Uses r12 to access the GOT 23d62589d5Swdenk */ 24d62589d5Swdenk 25d62589d5Swdenk#define START_GOT \ 26d62589d5Swdenk .section ".got2","aw"; \ 27d62589d5Swdenk.LCTOC1 = .+32768 28d62589d5Swdenk 29d62589d5Swdenk#define END_GOT \ 30d62589d5Swdenk .text 31d62589d5Swdenk 32d62589d5Swdenk#define GET_GOT \ 33d62589d5Swdenk bl 1f ; \ 34d62589d5Swdenk .text 2 ; \ 35d62589d5Swdenk0: .long .LCTOC1-1f ; \ 36d62589d5Swdenk .text ; \ 370f8aa159SJoakim Tjernlund1: mflr r12 ; \ 380f8aa159SJoakim Tjernlund lwz r0,0b-1b(r12) ; \ 390f8aa159SJoakim Tjernlund add r12,r0,r12 ; 40d62589d5Swdenk 41d62589d5Swdenk#define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME 42d62589d5Swdenk 430f8aa159SJoakim Tjernlund#define GOT(NAME) .L_ ## NAME (r12) 44d62589d5Swdenk 45d62589d5Swdenk 46d62589d5Swdenk/*************************************************************************** 47d62589d5Swdenk * Register names 48d62589d5Swdenk */ 49d62589d5Swdenk#define r0 0 50d62589d5Swdenk#define r1 1 51d62589d5Swdenk#define r2 2 52d62589d5Swdenk#define r3 3 53d62589d5Swdenk#define r4 4 54d62589d5Swdenk#define r5 5 55d62589d5Swdenk#define r6 6 56d62589d5Swdenk#define r7 7 57d62589d5Swdenk#define r8 8 58d62589d5Swdenk#define r9 9 59d62589d5Swdenk#define r10 10 60d62589d5Swdenk#define r11 11 61d62589d5Swdenk#define r12 12 62d62589d5Swdenk#define r13 13 63d62589d5Swdenk#define r14 14 64d62589d5Swdenk#define r15 15 65d62589d5Swdenk#define r16 16 66d62589d5Swdenk#define r17 17 67d62589d5Swdenk#define r18 18 68d62589d5Swdenk#define r19 19 69d62589d5Swdenk#define r20 20 70d62589d5Swdenk#define r21 21 71d62589d5Swdenk#define r22 22 72d62589d5Swdenk#define r23 23 73d62589d5Swdenk#define r24 24 74d62589d5Swdenk#define r25 25 75d62589d5Swdenk#define r26 26 76d62589d5Swdenk#define r27 27 77d62589d5Swdenk#define r28 28 78d62589d5Swdenk#define r29 29 79d62589d5Swdenk#define r30 30 80d62589d5Swdenk#define r31 31 81d62589d5Swdenk 82d62589d5Swdenk 83d62589d5Swdenk#if defined(CONFIG_8xx) || defined(CONFIG_MPC824X) 84d62589d5Swdenk 85d62589d5Swdenk/* Some special registers */ 86d62589d5Swdenk 87d62589d5Swdenk#define ICR 148 /* Interrupt Cause Register (37-44) */ 88d62589d5Swdenk#define DER 149 89d62589d5Swdenk#define COUNTA 150 /* Breakpoint Counter (37-44) */ 90d62589d5Swdenk#define COUNTB 151 /* Breakpoint Counter (37-44) */ 91d62589d5Swdenk#define LCTRL1 156 /* Load/Store Support (37-40) */ 92d62589d5Swdenk#define LCTRL2 157 /* Load/Store Support (37-41) */ 93d62589d5Swdenk#define ICTRL 158 94d62589d5Swdenk 95d62589d5Swdenk#endif /* CONFIG_8xx, CONFIG_MPC824X */ 96d62589d5Swdenk 970db5bca8Swdenk 980db5bca8Swdenk#if defined(CONFIG_5xx) 990db5bca8Swdenk/* Some special purpose registers */ 1000db5bca8Swdenk#define DER 149 /* Debug Enable Register */ 1010db5bca8Swdenk#define COUNTA 150 /* Breakpoint Counter */ 1020db5bca8Swdenk#define COUNTB 151 /* Breakpoint Counter */ 1030db5bca8Swdenk#define LCTRL1 156 /* Load/Store Support */ 1040db5bca8Swdenk#define LCTRL2 157 /* Load/Store Support */ 1050db5bca8Swdenk#define ICTRL 158 /* I-Bus Support Control Register */ 1060db5bca8Swdenk#define EID 81 1070db5bca8Swdenk#endif /* CONFIG_5xx */ 1080db5bca8Swdenk 109d62589d5Swdenk#if defined(CONFIG_8xx) 110d62589d5Swdenk 111d62589d5Swdenk/* Registers in the processor's internal memory map that we use. 112d62589d5Swdenk*/ 113d62589d5Swdenk#define SYPCR 0x00000004 114d62589d5Swdenk#define BR0 0x00000100 115d62589d5Swdenk#define OR0 0x00000104 116d62589d5Swdenk#define BR1 0x00000108 117d62589d5Swdenk#define OR1 0x0000010c 118d62589d5Swdenk#define BR2 0x00000110 119d62589d5Swdenk#define OR2 0x00000114 120d62589d5Swdenk#define BR3 0x00000118 121d62589d5Swdenk#define OR3 0x0000011c 122d62589d5Swdenk#define BR4 0x00000120 123d62589d5Swdenk#define OR4 0x00000124 124d62589d5Swdenk 125d62589d5Swdenk#define MAR 0x00000164 126d62589d5Swdenk#define MCR 0x00000168 127d62589d5Swdenk#define MAMR 0x00000170 128d62589d5Swdenk#define MBMR 0x00000174 129d62589d5Swdenk#define MSTAT 0x00000178 130d62589d5Swdenk#define MPTPR 0x0000017a 131d62589d5Swdenk#define MDR 0x0000017c 132d62589d5Swdenk 133d62589d5Swdenk#define TBSCR 0x00000200 134d62589d5Swdenk#define TBREFF0 0x00000204 135d62589d5Swdenk 136d62589d5Swdenk#define PLPRCR 0x00000284 137d62589d5Swdenk 138d62589d5Swdenk#elif defined(CONFIG_8260) 139d62589d5Swdenk 140d62589d5Swdenk#define HID2 1011 141d62589d5Swdenk 142d62589d5Swdenk#define HID0_IFEM (1<<7) 143d62589d5Swdenk 144d62589d5Swdenk#define HID0_ICE_BITPOS 16 145d62589d5Swdenk#define HID0_DCE_BITPOS 17 146d62589d5Swdenk 147d62589d5Swdenk#define IM_REGBASE 0x10000 148d62589d5Swdenk#define IM_SYPCR (IM_REGBASE+0x0004) 149d62589d5Swdenk#define IM_SWSR (IM_REGBASE+0x000e) 150d62589d5Swdenk#define IM_BR0 (IM_REGBASE+0x0100) 151d62589d5Swdenk#define IM_OR0 (IM_REGBASE+0x0104) 152d62589d5Swdenk#define IM_BR1 (IM_REGBASE+0x0108) 153d62589d5Swdenk#define IM_OR1 (IM_REGBASE+0x010c) 154d62589d5Swdenk#define IM_BR2 (IM_REGBASE+0x0110) 155d62589d5Swdenk#define IM_OR2 (IM_REGBASE+0x0114) 156d62589d5Swdenk#define IM_MPTPR (IM_REGBASE+0x0184) 157d62589d5Swdenk#define IM_PSDMR (IM_REGBASE+0x0190) 158d62589d5Swdenk#define IM_PSRT (IM_REGBASE+0x019c) 159d62589d5Swdenk#define IM_IMMR (IM_REGBASE+0x01a8) 160d62589d5Swdenk#define IM_SCCR (IM_REGBASE+0x0c80) 161d62589d5Swdenk 162d6ed3222SWolfgang Denk#elif defined(CONFIG_MPC5xxx) 163945af8d7Swdenk 164945af8d7Swdenk#define HID0_ICE_BITPOS 16 165945af8d7Swdenk#define HID0_DCE_BITPOS 17 166945af8d7Swdenk 167d62589d5Swdenk#endif 168d62589d5Swdenk 169d62589d5Swdenk#define curptr r2 170d62589d5Swdenk 171d62589d5Swdenk#define SYNC \ 172d62589d5Swdenk sync; \ 173d62589d5Swdenk isync 174d62589d5Swdenk 175d62589d5Swdenk/* 176d62589d5Swdenk * Macros for storing registers into and loading registers from 177d62589d5Swdenk * exception frames. 178d62589d5Swdenk */ 179d62589d5Swdenk#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 180d62589d5Swdenk#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 181d62589d5Swdenk#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 182d62589d5Swdenk#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 183d62589d5Swdenk#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 184d62589d5Swdenk#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 185d62589d5Swdenk#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 186d62589d5Swdenk#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 187d62589d5Swdenk#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 188d62589d5Swdenk#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 189d62589d5Swdenk 190d62589d5Swdenk/* 191d62589d5Swdenk * GCC sometimes accesses words at negative offsets from the stack 192d62589d5Swdenk * pointer, although the SysV ABI says it shouldn't. To cope with 193d62589d5Swdenk * this, we leave this much untouched space on the stack on exception 194d62589d5Swdenk * entry. 195d62589d5Swdenk */ 196d62589d5Swdenk#define STACK_UNDERHEAD 64 197d62589d5Swdenk 198d62589d5Swdenk/* 199d62589d5Swdenk * Exception entry code. This code runs with address translation 200d62589d5Swdenk * turned off, i.e. using physical addresses. 201d62589d5Swdenk * We assume sprg3 has the physical address of the current 202d62589d5Swdenk * task's thread_struct. 203d62589d5Swdenk */ 204efa35cf1SGrzegorz Bernacki#define EXCEPTION_PROLOG(reg1, reg2) \ 205d62589d5Swdenk mtspr SPRG0,r20; \ 206d62589d5Swdenk mtspr SPRG1,r21; \ 207d62589d5Swdenk mfcr r20; \ 208d62589d5Swdenk subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\ 209d62589d5Swdenk stw r20,_CCR(r21); /* save registers */ \ 210d62589d5Swdenk stw r22,GPR22(r21); \ 211d62589d5Swdenk stw r23,GPR23(r21); \ 212d62589d5Swdenk mfspr r20,SPRG0; \ 213d62589d5Swdenk stw r20,GPR20(r21); \ 214d62589d5Swdenk mfspr r22,SPRG1; \ 215d62589d5Swdenk stw r22,GPR21(r21); \ 216d62589d5Swdenk mflr r20; \ 217d62589d5Swdenk stw r20,_LINK(r21); \ 218d62589d5Swdenk mfctr r22; \ 219d62589d5Swdenk stw r22,_CTR(r21); \ 220d62589d5Swdenk mfspr r20,XER; \ 221d62589d5Swdenk stw r20,_XER(r21); \ 222cc3023b9SRafal Jaworowski mfspr r20, DAR_DEAR; \ 223efa35cf1SGrzegorz Bernacki stw r20,_DAR(r21); \ 224efa35cf1SGrzegorz Bernacki mfspr r22,reg1; \ 225efa35cf1SGrzegorz Bernacki mfspr r23,reg2; \ 226d62589d5Swdenk stw r0,GPR0(r21); \ 227d62589d5Swdenk stw r1,GPR1(r21); \ 228d62589d5Swdenk stw r2,GPR2(r21); \ 229d62589d5Swdenk stw r1,0(r21); \ 230d62589d5Swdenk mr r1,r21; /* set new kernel sp */ \ 231d62589d5Swdenk SAVE_4GPRS(3, r21); 232d62589d5Swdenk/* 233d62589d5Swdenk * Note: code which follows this uses cr0.eq (set if from kernel), 234d62589d5Swdenk * r21, r22 (SRR0), and r23 (SRR1). 235d62589d5Swdenk */ 236d62589d5Swdenk 237d62589d5Swdenk/* 238d62589d5Swdenk * Exception vectors. 239d62589d5Swdenk * 240d62589d5Swdenk * The data words for `hdlr' and `int_return' are initialized with 241d62589d5Swdenk * OFFSET values only; they must be relocated first before they can 242d62589d5Swdenk * be used! 243d62589d5Swdenk */ 244fc4e1887SJoakim Tjernlund#define COPY_EE(d, s) rlwimi d,s,0,16,16 245fc4e1887SJoakim Tjernlund#define NOCOPY(d, s) 246fc4e1887SJoakim Tjernlund#define EXC_XFER_TEMPLATE(label, hdlr, msr, copyee) \ 247fc4e1887SJoakim Tjernlund bl 1f; \ 248fc4e1887SJoakim Tjernlund1: mflr r20; \ 249fc4e1887SJoakim Tjernlund lwz r20,(.L_ ## label)-1b+8(r20); \ 250fc4e1887SJoakim Tjernlund mtlr r20; \ 251fc4e1887SJoakim Tjernlund li r20,msr; \ 252fc4e1887SJoakim Tjernlund copyee(r20,r23); \ 253d62589d5Swdenk rlwimi r20,r23,0,25,25; \ 254d62589d5Swdenk blrl; \ 255d62589d5Swdenk.L_ ## label : \ 256efa35cf1SGrzegorz Bernacki .long hdlr - _start + _START_OFFSET; \ 257fc4e1887SJoakim Tjernlund .long int_return - _start + _START_OFFSET; \ 258fc4e1887SJoakim Tjernlund .long transfer_to_handler - _start + _START_OFFSET 259fc4e1887SJoakim Tjernlund 260fc4e1887SJoakim Tjernlund#define STD_EXCEPTION(n, label, hdlr) \ 261fc4e1887SJoakim Tjernlund . = n; \ 262fc4e1887SJoakim Tjernlundlabel: \ 263fc4e1887SJoakim Tjernlund EXCEPTION_PROLOG(SRR0, SRR1); \ 264fc4e1887SJoakim Tjernlund addi r3,r1,STACK_FRAME_OVERHEAD; \ 265fc4e1887SJoakim Tjernlund EXC_XFER_TEMPLATE(label, hdlr, MSR_KERNEL, NOCOPY) \ 266d62589d5Swdenk 267d62589d5Swdenk#define CRIT_EXCEPTION(n, label, hdlr) \ 268d62589d5Swdenk . = n; \ 269d62589d5Swdenklabel: \ 27002032e8fSRafal Jaworowski EXCEPTION_PROLOG(CSRR0, CSRR1); \ 271d62589d5Swdenk addi r3,r1,STACK_FRAME_OVERHEAD; \ 272fc4e1887SJoakim Tjernlund EXC_XFER_TEMPLATE(label, hdlr, \ 273fc4e1887SJoakim Tjernlund MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \ 274efa35cf1SGrzegorz Bernacki 275efa35cf1SGrzegorz Bernacki#define MCK_EXCEPTION(n, label, hdlr) \ 276efa35cf1SGrzegorz Bernacki . = n; \ 277efa35cf1SGrzegorz Bernackilabel: \ 278efa35cf1SGrzegorz Bernacki EXCEPTION_PROLOG(MCSRR0, MCSRR1); \ 279efa35cf1SGrzegorz Bernacki addi r3,r1,STACK_FRAME_OVERHEAD; \ 280fc4e1887SJoakim Tjernlund EXC_XFER_TEMPLATE(label, hdlr, \ 281fc4e1887SJoakim Tjernlund MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE), NOCOPY) \ 282d62589d5Swdenk 283d62589d5Swdenk#endif /* __PPC_ASM_TMPL__ */ 284