1d62589d5Swdenk/* 2d62589d5Swdenk * (C) Copyright 2000-2002 3d62589d5Swdenk * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4d62589d5Swdenk * 5d62589d5Swdenk * See file CREDITS for list of people who contributed to this 6d62589d5Swdenk * project. 7d62589d5Swdenk * 8d62589d5Swdenk * This program is free software; you can redistribute it and/or 9d62589d5Swdenk * modify it under the terms of the GNU General Public License as 10d62589d5Swdenk * published by the Free Software Foundation; either version 2 of 11d62589d5Swdenk * the License, or (at your option) any later version. 12d62589d5Swdenk * 13d62589d5Swdenk * This program is distributed in the hope that it will be useful, 14d62589d5Swdenk * but WITHOUT ANY WARRANTY; without even the implied warranty of 15d62589d5Swdenk * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16d62589d5Swdenk * GNU General Public License for more details. 17d62589d5Swdenk * 18d62589d5Swdenk * You should have received a copy of the GNU General Public License 19d62589d5Swdenk * along with this program; if not, write to the Free Software 20d62589d5Swdenk * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21d62589d5Swdenk * MA 02111-1307 USA 22d62589d5Swdenk */ 23d62589d5Swdenk 24d62589d5Swdenk/* 25d62589d5Swdenk * This file contains all the macros and symbols which define 26d62589d5Swdenk * a PowerPC assembly language environment. 27d62589d5Swdenk */ 28d62589d5Swdenk#ifndef __PPC_ASM_TMPL__ 29d62589d5Swdenk#define __PPC_ASM_TMPL__ 30d62589d5Swdenk 31d62589d5Swdenk/*************************************************************************** 32d62589d5Swdenk * 33d62589d5Swdenk * These definitions simplify the ugly declarations necessary for GOT 34d62589d5Swdenk * definitions. 35d62589d5Swdenk * 36d62589d5Swdenk * Stolen from prepboot/bootldr.h, (C) 1998 Gabriel Paubert, paubert@iram.es 37d62589d5Swdenk * 38d62589d5Swdenk * Uses r14 to access the GOT 39d62589d5Swdenk */ 40d62589d5Swdenk 41d62589d5Swdenk#define START_GOT \ 42d62589d5Swdenk .section ".got2","aw"; \ 43d62589d5Swdenk.LCTOC1 = .+32768 44d62589d5Swdenk 45d62589d5Swdenk#define END_GOT \ 46d62589d5Swdenk .text 47d62589d5Swdenk 48d62589d5Swdenk#define GET_GOT \ 49d62589d5Swdenk bl 1f ; \ 50d62589d5Swdenk .text 2 ; \ 51d62589d5Swdenk0: .long .LCTOC1-1f ; \ 52d62589d5Swdenk .text ; \ 53d62589d5Swdenk1: mflr r14 ; \ 54d62589d5Swdenk lwz r0,0b-1b(r14) ; \ 55d62589d5Swdenk add r14,r0,r14 ; 56d62589d5Swdenk 57d62589d5Swdenk#define GOT_ENTRY(NAME) .L_ ## NAME = . - .LCTOC1 ; .long NAME 58d62589d5Swdenk 59d62589d5Swdenk#define GOT(NAME) .L_ ## NAME (r14) 60d62589d5Swdenk 61d62589d5Swdenk 62d62589d5Swdenk/*************************************************************************** 63d62589d5Swdenk * Register names 64d62589d5Swdenk */ 65d62589d5Swdenk#define r0 0 66d62589d5Swdenk#define r1 1 67d62589d5Swdenk#define r2 2 68d62589d5Swdenk#define r3 3 69d62589d5Swdenk#define r4 4 70d62589d5Swdenk#define r5 5 71d62589d5Swdenk#define r6 6 72d62589d5Swdenk#define r7 7 73d62589d5Swdenk#define r8 8 74d62589d5Swdenk#define r9 9 75d62589d5Swdenk#define r10 10 76d62589d5Swdenk#define r11 11 77d62589d5Swdenk#define r12 12 78d62589d5Swdenk#define r13 13 79d62589d5Swdenk#define r14 14 80d62589d5Swdenk#define r15 15 81d62589d5Swdenk#define r16 16 82d62589d5Swdenk#define r17 17 83d62589d5Swdenk#define r18 18 84d62589d5Swdenk#define r19 19 85d62589d5Swdenk#define r20 20 86d62589d5Swdenk#define r21 21 87d62589d5Swdenk#define r22 22 88d62589d5Swdenk#define r23 23 89d62589d5Swdenk#define r24 24 90d62589d5Swdenk#define r25 25 91d62589d5Swdenk#define r26 26 92d62589d5Swdenk#define r27 27 93d62589d5Swdenk#define r28 28 94d62589d5Swdenk#define r29 29 95d62589d5Swdenk#define r30 30 96d62589d5Swdenk#define r31 31 97d62589d5Swdenk 98d62589d5Swdenk 99d62589d5Swdenk#if defined(CONFIG_8xx) || defined(CONFIG_MPC824X) 100d62589d5Swdenk 101d62589d5Swdenk/* Some special registers */ 102d62589d5Swdenk 103d62589d5Swdenk#define ICR 148 /* Interrupt Cause Register (37-44) */ 104d62589d5Swdenk#define DER 149 105d62589d5Swdenk#define COUNTA 150 /* Breakpoint Counter (37-44) */ 106d62589d5Swdenk#define COUNTB 151 /* Breakpoint Counter (37-44) */ 107d62589d5Swdenk#define LCTRL1 156 /* Load/Store Support (37-40) */ 108d62589d5Swdenk#define LCTRL2 157 /* Load/Store Support (37-41) */ 109d62589d5Swdenk#define ICTRL 158 110d62589d5Swdenk 111d62589d5Swdenk#endif /* CONFIG_8xx, CONFIG_MPC824X */ 112d62589d5Swdenk 113*0db5bca8Swdenk 114*0db5bca8Swdenk#if defined(CONFIG_5xx) 115*0db5bca8Swdenk/* Some special purpose registers */ 116*0db5bca8Swdenk#define DER 149 /* Debug Enable Register */ 117*0db5bca8Swdenk#define COUNTA 150 /* Breakpoint Counter */ 118*0db5bca8Swdenk#define COUNTB 151 /* Breakpoint Counter */ 119*0db5bca8Swdenk#define LCTRL1 156 /* Load/Store Support */ 120*0db5bca8Swdenk#define LCTRL2 157 /* Load/Store Support */ 121*0db5bca8Swdenk#define ICTRL 158 /* I-Bus Support Control Register */ 122*0db5bca8Swdenk#define EID 81 123*0db5bca8Swdenk#endif /* CONFIG_5xx */ 124*0db5bca8Swdenk 125d62589d5Swdenk#if defined(CONFIG_8xx) 126d62589d5Swdenk 127d62589d5Swdenk/* Registers in the processor's internal memory map that we use. 128d62589d5Swdenk*/ 129d62589d5Swdenk#define SYPCR 0x00000004 130d62589d5Swdenk#define BR0 0x00000100 131d62589d5Swdenk#define OR0 0x00000104 132d62589d5Swdenk#define BR1 0x00000108 133d62589d5Swdenk#define OR1 0x0000010c 134d62589d5Swdenk#define BR2 0x00000110 135d62589d5Swdenk#define OR2 0x00000114 136d62589d5Swdenk#define BR3 0x00000118 137d62589d5Swdenk#define OR3 0x0000011c 138d62589d5Swdenk#define BR4 0x00000120 139d62589d5Swdenk#define OR4 0x00000124 140d62589d5Swdenk 141d62589d5Swdenk#define MAR 0x00000164 142d62589d5Swdenk#define MCR 0x00000168 143d62589d5Swdenk#define MAMR 0x00000170 144d62589d5Swdenk#define MBMR 0x00000174 145d62589d5Swdenk#define MSTAT 0x00000178 146d62589d5Swdenk#define MPTPR 0x0000017a 147d62589d5Swdenk#define MDR 0x0000017c 148d62589d5Swdenk 149d62589d5Swdenk#define TBSCR 0x00000200 150d62589d5Swdenk#define TBREFF0 0x00000204 151d62589d5Swdenk 152d62589d5Swdenk#define PLPRCR 0x00000284 153d62589d5Swdenk 154d62589d5Swdenk#elif defined(CONFIG_8260) 155d62589d5Swdenk 156d62589d5Swdenk#define HID2 1011 157d62589d5Swdenk 158d62589d5Swdenk#define HID0_IFEM (1<<7) 159d62589d5Swdenk 160d62589d5Swdenk#define HID0_ICE_BITPOS 16 161d62589d5Swdenk#define HID0_DCE_BITPOS 17 162d62589d5Swdenk 163d62589d5Swdenk#define IM_REGBASE 0x10000 164d62589d5Swdenk#define IM_SYPCR (IM_REGBASE+0x0004) 165d62589d5Swdenk#define IM_SWSR (IM_REGBASE+0x000e) 166d62589d5Swdenk#define IM_BR0 (IM_REGBASE+0x0100) 167d62589d5Swdenk#define IM_OR0 (IM_REGBASE+0x0104) 168d62589d5Swdenk#define IM_BR1 (IM_REGBASE+0x0108) 169d62589d5Swdenk#define IM_OR1 (IM_REGBASE+0x010c) 170d62589d5Swdenk#define IM_BR2 (IM_REGBASE+0x0110) 171d62589d5Swdenk#define IM_OR2 (IM_REGBASE+0x0114) 172d62589d5Swdenk#define IM_MPTPR (IM_REGBASE+0x0184) 173d62589d5Swdenk#define IM_PSDMR (IM_REGBASE+0x0190) 174d62589d5Swdenk#define IM_PSRT (IM_REGBASE+0x019c) 175d62589d5Swdenk#define IM_IMMR (IM_REGBASE+0x01a8) 176d62589d5Swdenk#define IM_SCCR (IM_REGBASE+0x0c80) 177d62589d5Swdenk 178d62589d5Swdenk#endif 179d62589d5Swdenk 180d62589d5Swdenk#define curptr r2 181d62589d5Swdenk 182d62589d5Swdenk#define SYNC \ 183d62589d5Swdenk sync; \ 184d62589d5Swdenk isync 185d62589d5Swdenk 186d62589d5Swdenk/* 187d62589d5Swdenk * Macros for storing registers into and loading registers from 188d62589d5Swdenk * exception frames. 189d62589d5Swdenk */ 190d62589d5Swdenk#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) 191d62589d5Swdenk#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) 192d62589d5Swdenk#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) 193d62589d5Swdenk#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) 194d62589d5Swdenk#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) 195d62589d5Swdenk#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) 196d62589d5Swdenk#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) 197d62589d5Swdenk#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) 198d62589d5Swdenk#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) 199d62589d5Swdenk#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) 200d62589d5Swdenk 201d62589d5Swdenk/* 202d62589d5Swdenk * GCC sometimes accesses words at negative offsets from the stack 203d62589d5Swdenk * pointer, although the SysV ABI says it shouldn't. To cope with 204d62589d5Swdenk * this, we leave this much untouched space on the stack on exception 205d62589d5Swdenk * entry. 206d62589d5Swdenk */ 207d62589d5Swdenk#define STACK_UNDERHEAD 64 208d62589d5Swdenk 209d62589d5Swdenk/* 210d62589d5Swdenk * Exception entry code. This code runs with address translation 211d62589d5Swdenk * turned off, i.e. using physical addresses. 212d62589d5Swdenk * We assume sprg3 has the physical address of the current 213d62589d5Swdenk * task's thread_struct. 214d62589d5Swdenk */ 215d62589d5Swdenk#define EXCEPTION_PROLOG \ 216d62589d5Swdenk mtspr SPRG0,r20; \ 217d62589d5Swdenk mtspr SPRG1,r21; \ 218d62589d5Swdenk mfcr r20; \ 219d62589d5Swdenk subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\ 220d62589d5Swdenk stw r20,_CCR(r21); /* save registers */ \ 221d62589d5Swdenk stw r22,GPR22(r21); \ 222d62589d5Swdenk stw r23,GPR23(r21); \ 223d62589d5Swdenk mfspr r20,SPRG0; \ 224d62589d5Swdenk stw r20,GPR20(r21); \ 225d62589d5Swdenk mfspr r22,SPRG1; \ 226d62589d5Swdenk stw r22,GPR21(r21); \ 227d62589d5Swdenk mflr r20; \ 228d62589d5Swdenk stw r20,_LINK(r21); \ 229d62589d5Swdenk mfctr r22; \ 230d62589d5Swdenk stw r22,_CTR(r21); \ 231d62589d5Swdenk mfspr r20,XER; \ 232d62589d5Swdenk stw r20,_XER(r21); \ 233d62589d5Swdenk mfspr r22,SRR0; \ 234d62589d5Swdenk mfspr r23,SRR1; \ 235d62589d5Swdenk stw r0,GPR0(r21); \ 236d62589d5Swdenk stw r1,GPR1(r21); \ 237d62589d5Swdenk stw r2,GPR2(r21); \ 238d62589d5Swdenk stw r1,0(r21); \ 239d62589d5Swdenk mr r1,r21; /* set new kernel sp */ \ 240d62589d5Swdenk SAVE_4GPRS(3, r21); 241d62589d5Swdenk/* 242d62589d5Swdenk * Note: code which follows this uses cr0.eq (set if from kernel), 243d62589d5Swdenk * r21, r22 (SRR0), and r23 (SRR1). 244d62589d5Swdenk */ 245d62589d5Swdenk 246d62589d5Swdenk/* 247d62589d5Swdenk * Critical exception entry code. This is just like the other exception 248d62589d5Swdenk * code except that it uses SRR2 and SRR3 instead of SRR0 and SRR1. 249d62589d5Swdenk */ 250d62589d5Swdenk#define CRITICAL_EXCEPTION_PROLOG \ 251d62589d5Swdenk mtspr SPRG0,r20; \ 252d62589d5Swdenk mtspr SPRG1,r21; \ 253d62589d5Swdenk mfcr r20; \ 254d62589d5Swdenk subi r21,r1,INT_FRAME_SIZE+STACK_UNDERHEAD; /* alloc exc. frame */\ 255d62589d5Swdenk stw r20,_CCR(r21); /* save registers */ \ 256d62589d5Swdenk stw r22,GPR22(r21); \ 257d62589d5Swdenk stw r23,GPR23(r21); \ 258d62589d5Swdenk mfspr r20,SPRG0; \ 259d62589d5Swdenk stw r20,GPR20(r21); \ 260d62589d5Swdenk mfspr r22,SPRG1; \ 261d62589d5Swdenk stw r22,GPR21(r21); \ 262d62589d5Swdenk mflr r20; \ 263d62589d5Swdenk stw r20,_LINK(r21); \ 264d62589d5Swdenk mfctr r22; \ 265d62589d5Swdenk stw r22,_CTR(r21); \ 266d62589d5Swdenk mfspr r20,XER; \ 267d62589d5Swdenk stw r20,_XER(r21); \ 268d62589d5Swdenk mfspr r22,990; /* SRR2 */ \ 269d62589d5Swdenk mfspr r23,991; /* SRR3 */ \ 270d62589d5Swdenk stw r0,GPR0(r21); \ 271d62589d5Swdenk stw r1,GPR1(r21); \ 272d62589d5Swdenk stw r2,GPR2(r21); \ 273d62589d5Swdenk stw r1,0(r21); \ 274d62589d5Swdenk mr r1,r21; /* set new kernel sp */ \ 275d62589d5Swdenk SAVE_4GPRS(3, r21); 276d62589d5Swdenk/* 277d62589d5Swdenk * Note: code which follows this uses cr0.eq (set if from kernel), 278d62589d5Swdenk * r21, r22 (SRR2), and r23 (SRR3). 279d62589d5Swdenk */ 280d62589d5Swdenk 281d62589d5Swdenk/* 282d62589d5Swdenk * Exception vectors. 283d62589d5Swdenk * 284d62589d5Swdenk * The data words for `hdlr' and `int_return' are initialized with 285d62589d5Swdenk * OFFSET values only; they must be relocated first before they can 286d62589d5Swdenk * be used! 287d62589d5Swdenk */ 288d62589d5Swdenk#define STD_EXCEPTION(n, label, hdlr) \ 289d62589d5Swdenk . = n; \ 290d62589d5Swdenklabel: \ 291d62589d5Swdenk EXCEPTION_PROLOG; \ 292d62589d5Swdenk lwz r3,GOT(transfer_to_handler); \ 293d62589d5Swdenk mtlr r3; \ 294d62589d5Swdenk addi r3,r1,STACK_FRAME_OVERHEAD; \ 295d62589d5Swdenk li r20,MSR_KERNEL; \ 296d62589d5Swdenk rlwimi r20,r23,0,25,25; \ 297d62589d5Swdenk blrl ; \ 298d62589d5Swdenk.L_ ## label : \ 299d62589d5Swdenk .long hdlr - _start + EXC_OFF_SYS_RESET; \ 300d62589d5Swdenk .long int_return - _start + EXC_OFF_SYS_RESET 301d62589d5Swdenk 302d62589d5Swdenk 303d62589d5Swdenk#define CRIT_EXCEPTION(n, label, hdlr) \ 304d62589d5Swdenk . = n; \ 305d62589d5Swdenklabel: \ 306d62589d5Swdenk CRITICAL_EXCEPTION_PROLOG; \ 307d62589d5Swdenk lwz r3,GOT(transfer_to_handler); \ 308d62589d5Swdenk mtlr r3; \ 309d62589d5Swdenk addi r3,r1,STACK_FRAME_OVERHEAD; \ 310d62589d5Swdenk li r20,MSR_KERNEL; \ 311d62589d5Swdenk rlwimi r20,r23,0,25,25; \ 312d62589d5Swdenk blrl ; \ 313d62589d5Swdenk.L_ ## label : \ 314d62589d5Swdenk .long hdlr - _start + EXC_OFF_SYS_RESET; \ 315d62589d5Swdenk .long crit_return - _start + EXC_OFF_SYS_RESET 316d62589d5Swdenk 317d62589d5Swdenk#endif /* __PPC_ASM_TMPL__ */ 318