1*b04601a7SPhilip, Avinash /* 2*b04601a7SPhilip, Avinash * (C) Copyright 2011-2013 3*b04601a7SPhilip, Avinash * Texas Instruments, <www.ti.com> 4*b04601a7SPhilip, Avinash * 5*b04601a7SPhilip, Avinash * SPDX-License-Identifier: GPL-2.0+ 6*b04601a7SPhilip, Avinash * 7*b04601a7SPhilip, Avinash * For more details, please see the TRM at http://www.ti.com/product/tps65910 8*b04601a7SPhilip, Avinash */ 9*b04601a7SPhilip, Avinash #ifndef __POWER_TPS65910_H__ 10*b04601a7SPhilip, Avinash #define __POWER_TPS65910_H__ 11*b04601a7SPhilip, Avinash 12*b04601a7SPhilip, Avinash #define MPU 0 13*b04601a7SPhilip, Avinash #define CORE 1 14*b04601a7SPhilip, Avinash 15*b04601a7SPhilip, Avinash #define TPS65910_SR_I2C_ADDR 0x12 16*b04601a7SPhilip, Avinash #define TPS65910_CTRL_I2C_ADDR 0x2D 17*b04601a7SPhilip, Avinash 18*b04601a7SPhilip, Avinash /* PMIC Register offsets */ 19*b04601a7SPhilip, Avinash enum { 20*b04601a7SPhilip, Avinash TPS65910_VDD1_REG = 0x21, 21*b04601a7SPhilip, Avinash TPS65910_VDD1_OP_REG = 0x22, 22*b04601a7SPhilip, Avinash TPS65910_VDD2_REG = 0x24, 23*b04601a7SPhilip, Avinash TPS65910_VDD2_OP_REG = 0x25, 24*b04601a7SPhilip, Avinash TPS65910_DEVCTRL_REG = 0x3F, 25*b04601a7SPhilip, Avinash }; 26*b04601a7SPhilip, Avinash 27*b04601a7SPhilip, Avinash /* VDD2 & VDD1 control register (VDD2_REG & VDD1_REG) */ 28*b04601a7SPhilip, Avinash #define TPS65910_VGAIN_SEL_MASK (0x3 << 6) 29*b04601a7SPhilip, Avinash #define TPS65910_ILMAX_MASK (0x1 << 5) 30*b04601a7SPhilip, Avinash #define TPS65910_TSTEP_MASK (0x7 << 2) 31*b04601a7SPhilip, Avinash #define TPS65910_ST_MASK (0x3) 32*b04601a7SPhilip, Avinash 33*b04601a7SPhilip, Avinash #define TPS65910_REG_VGAIN_SEL_X1 (0x0 << 6) 34*b04601a7SPhilip, Avinash #define TPS65910_REG_VGAIN_SEL_X1_0 (0x1 << 6) 35*b04601a7SPhilip, Avinash #define TPS65910_REG_VGAIN_SEL_X3 (0x2 << 6) 36*b04601a7SPhilip, Avinash #define TPS65910_REG_VGAIN_SEL_X4 (0x3 << 6) 37*b04601a7SPhilip, Avinash 38*b04601a7SPhilip, Avinash #define TPS65910_REG_ILMAX_1_0_A (0x0 << 5) 39*b04601a7SPhilip, Avinash #define TPS65910_REG_ILMAX_1_5_A (0x1 << 5) 40*b04601a7SPhilip, Avinash 41*b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_ (0x0 << 2) 42*b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_12_5 (0x1 << 2) 43*b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_9_4 (0x2 << 2) 44*b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_7_5 (0x3 << 2) 45*b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_6_25 (0x4 << 2) 46*b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_4_7 (0x5 << 2) 47*b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_3_12 (0x6 << 2) 48*b04601a7SPhilip, Avinash #define TPS65910_REG_TSTEP_2_5 (0x7 << 2) 49*b04601a7SPhilip, Avinash 50*b04601a7SPhilip, Avinash #define TPS65910_REG_ST_OFF (0x0) 51*b04601a7SPhilip, Avinash #define TPS65910_REG_ST_ON_HI_POW (0x1) 52*b04601a7SPhilip, Avinash #define TPS65910_REG_ST_OFF_1 (0x2) 53*b04601a7SPhilip, Avinash #define TPS65910_REG_ST_ON_LOW_POW (0x3) 54*b04601a7SPhilip, Avinash 55*b04601a7SPhilip, Avinash 56*b04601a7SPhilip, Avinash /* VDD2 & VDD1 voltage selection register. (VDD2_OP_REG & VDD1_OP_REG) */ 57*b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL (0x7F) 58*b04601a7SPhilip, Avinash 59*b04601a7SPhilip, Avinash #define TPS65910_OP_REG_CMD_MASK (0x1 << 7) 60*b04601a7SPhilip, Avinash #define TPS65910_OP_REG_CMD_OP (0x0 << 7) 61*b04601a7SPhilip, Avinash #define TPS65910_OP_REG_CMD_SR (0x1 << 7) 62*b04601a7SPhilip, Avinash 63*b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL_MASK (0x7F) 64*b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL_0_9_5 (0x1F) /* 0.9500 V */ 65*b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL_1_1_3 (0x2E) /* 1.1375 V */ 66*b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL_1_2_0 (0x33) /* 1.2000 V */ 67*b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL_1_2_6 (0x38) /* 1.2625 V */ 68*b04601a7SPhilip, Avinash #define TPS65910_OP_REG_SEL_1_3_2_5 (0x3D) /* 1.3250 V */ 69*b04601a7SPhilip, Avinash 70*b04601a7SPhilip, Avinash /* Device control register . (DEVCTRL_REG) */ 71*b04601a7SPhilip, Avinash #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_MASK (0x1 << 4) 72*b04601a7SPhilip, Avinash #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_SR_I2C (0x0 << 4) 73*b04601a7SPhilip, Avinash #define TPS65910_DEVCTRL_REG_SR_CTL_I2C_SEL_CTL_I2C (0x1 << 4) 74*b04601a7SPhilip, Avinash 75*b04601a7SPhilip, Avinash int tps65910_set_i2c_control(void); 76*b04601a7SPhilip, Avinash int tps65910_voltage_update(unsigned int module, unsigned char vddx_op_vol_sel); 77*b04601a7SPhilip, Avinash #endif /* __POWER_TPS65910_H__ */ 78