1*86db550bSTom Rini /* 2*86db550bSTom Rini * (C) Copyright 2014 3*86db550bSTom Rini * Texas Instruments, <www.ti.com> 4*86db550bSTom Rini * 5*86db550bSTom Rini * SPDX-License-Identifier: GPL-2.0+ 6*86db550bSTom Rini */ 7*86db550bSTom Rini 8*86db550bSTom Rini #ifndef __POWER_TPS65218_H__ 9*86db550bSTom Rini #define __POWER_TPS65218_H__ 10*86db550bSTom Rini 11*86db550bSTom Rini /* I2C chip address */ 12*86db550bSTom Rini #define TPS65218_CHIP_PM 0x24 13*86db550bSTom Rini 14*86db550bSTom Rini /* Registers */ 15*86db550bSTom Rini enum { 16*86db550bSTom Rini TPS65218_CHIPID = 0x00, 17*86db550bSTom Rini TPS65218_INT1, 18*86db550bSTom Rini TPS65218_INT2, 19*86db550bSTom Rini TPS65218_INT_MASK1, 20*86db550bSTom Rini TPS65218_INT_MASK2, 21*86db550bSTom Rini TPS65218_STATUS, 22*86db550bSTom Rini TPS65218_CONTROL, 23*86db550bSTom Rini TPS65218_FLAG, 24*86db550bSTom Rini TPS65218_PASSWORD = 0x10, 25*86db550bSTom Rini TPS65218_ENABLE1, 26*86db550bSTom Rini TPS65218_ENABLE2, 27*86db550bSTom Rini TPS65218_CONFIG1, 28*86db550bSTom Rini TPS65218_CONFIG2, 29*86db550bSTom Rini TPS65218_CONFIG3, 30*86db550bSTom Rini TPS65218_DCDC1, 31*86db550bSTom Rini TPS65218_DCDC2, 32*86db550bSTom Rini TPS65218_DCDC3, 33*86db550bSTom Rini TPS65218_DCDC4, 34*86db550bSTom Rini TPS65218_SLEW, 35*86db550bSTom Rini TPS65218_LDO1, 36*86db550bSTom Rini TPS65218_SEQ1 = 0x20, 37*86db550bSTom Rini TPS65218_SEQ2, 38*86db550bSTom Rini TPS65218_SEQ3, 39*86db550bSTom Rini TPS65218_SEQ4, 40*86db550bSTom Rini TPS65218_SEQ5, 41*86db550bSTom Rini TPS65218_SEQ6, 42*86db550bSTom Rini TPS65218_SEQ7, 43*86db550bSTom Rini TPS65218_PMIC_NUM_OF_REGS, 44*86db550bSTom Rini }; 45*86db550bSTom Rini 46*86db550bSTom Rini #define TPS65218_PROT_LEVEL_NONE 0x00 47*86db550bSTom Rini #define TPS65218_PROT_LEVEL_1 0x01 48*86db550bSTom Rini #define TPS65218_PROT_LEVEL_2 0x02 49*86db550bSTom Rini 50*86db550bSTom Rini #define TPS65218_PASSWORD_LOCK_FOR_WRITE 0x00 51*86db550bSTom Rini #define TPS65218_PASSWORD_UNLOCK 0x7D 52*86db550bSTom Rini 53*86db550bSTom Rini #define TPS65218_DCDC_GO 0x80 54*86db550bSTom Rini 55*86db550bSTom Rini #define TPS65218_MASK_ALL_BITS 0xFF 56*86db550bSTom Rini 57*86db550bSTom Rini #define TPS65218_DCDC_VOLT_SEL_1100MV 0x19 58*86db550bSTom Rini #define TPS65218_DCDC_VOLT_SEL_1330MV 0x30 59*86db550bSTom Rini 60*86db550bSTom Rini int tps65218_reg_write(uchar prot_level, uchar dest_reg, uchar dest_val, 61*86db550bSTom Rini uchar mask); 62*86db550bSTom Rini int tps65218_voltage_update(uchar dc_cntrl_reg, uchar volt_sel); 63*86db550bSTom Rini #endif /* __POWER_TPS65218_H__ */ 64