1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2151b223bSSimon Glass /* 3151b223bSSimon Glass * Copyright (c) 2015 Google, Inc 4151b223bSSimon Glass * Written by Simon Glass <sjg@chromium.org> 5151b223bSSimon Glass */ 6151b223bSSimon Glass 7151b223bSSimon Glass #ifndef __TPS65090_PMIC_H_ 8151b223bSSimon Glass #define __TPS65090_PMIC_H_ 9151b223bSSimon Glass 10151b223bSSimon Glass /* I2C device address for TPS65090 PMU */ 11151b223bSSimon Glass #define TPS65090_I2C_ADDR 0x48 12151b223bSSimon Glass 13151b223bSSimon Glass /* TPS65090 register addresses */ 14151b223bSSimon Glass enum { 15151b223bSSimon Glass REG_IRQ1 = 0, 16151b223bSSimon Glass REG_CG_CTRL0 = 4, 17151b223bSSimon Glass REG_CG_STATUS1 = 0xa, 18151b223bSSimon Glass REG_FET_BASE = 0xe, /* Not a real register, FETs count from here */ 19151b223bSSimon Glass REG_FET1_CTRL, 20151b223bSSimon Glass REG_FET2_CTRL, 21151b223bSSimon Glass REG_FET3_CTRL, 22151b223bSSimon Glass REG_FET4_CTRL, 23151b223bSSimon Glass REG_FET5_CTRL, 24151b223bSSimon Glass REG_FET6_CTRL, 25151b223bSSimon Glass REG_FET7_CTRL, 26151b223bSSimon Glass TPS65090_NUM_REGS, 27151b223bSSimon Glass }; 28151b223bSSimon Glass 29151b223bSSimon Glass enum { 30151b223bSSimon Glass IRQ1_VBATG = 1 << 3, 31151b223bSSimon Glass CG_CTRL0_ENC_MASK = 0x01, 32151b223bSSimon Glass 33151b223bSSimon Glass MAX_FET_NUM = 7, 34151b223bSSimon Glass MAX_CTRL_READ_TRIES = 5, 35151b223bSSimon Glass 36151b223bSSimon Glass /* TPS65090 FET_CTRL register values */ 37151b223bSSimon Glass FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ 38151b223bSSimon Glass FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ 39151b223bSSimon Glass FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ 40151b223bSSimon Glass FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ 41151b223bSSimon Glass FET_CTRL_ENFET = 1 << 0, /* Enable FET */ 42151b223bSSimon Glass }; 43151b223bSSimon Glass 44151b223bSSimon Glass enum { 45151b223bSSimon Glass /* Status register fields */ 46151b223bSSimon Glass TPS65090_ST1_OTC = 1 << 0, 47151b223bSSimon Glass TPS65090_ST1_OCC = 1 << 1, 48151b223bSSimon Glass TPS65090_ST1_STATE_SHIFT = 4, 49151b223bSSimon Glass TPS65090_ST1_STATE_MASK = 0xf << TPS65090_ST1_STATE_SHIFT, 50151b223bSSimon Glass }; 51151b223bSSimon Glass 52151b223bSSimon Glass /* Drivers name */ 53151b223bSSimon Glass #define TPS65090_FET_DRIVER "tps65090_fet" 54151b223bSSimon Glass 55151b223bSSimon Glass #endif /* __TPS65090_PMIC_H_ */ 56