1 /* 2 * Copyright (c) 2015 Google, Inc 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __S5M8767_H_ 8 #define __S5M8767_H_ 9 10 enum s5m8767_regnum { 11 S5M8767_BUCK1 = 0, 12 S5M8767_BUCK2, 13 S5M8767_BUCK3, 14 S5M8767_BUCK4, 15 S5M8767_BUCK5, 16 S5M8767_BUCK6, 17 S5M8767_BUCK7, 18 S5M8767_BUCK8, 19 S5M8767_BUCK9, 20 S5M8767_LDO1, 21 S5M8767_LDO2, 22 S5M8767_LDO3, 23 S5M8767_LDO4, 24 S5M8767_LDO5, 25 S5M8767_LDO6, 26 S5M8767_LDO7, 27 S5M8767_LDO8, 28 S5M8767_LDO9, 29 S5M8767_LDO10, 30 S5M8767_LDO11, 31 S5M8767_LDO12, 32 S5M8767_LDO13, 33 S5M8767_LDO14, 34 S5M8767_LDO15, 35 S5M8767_LDO16, 36 S5M8767_LDO17, 37 S5M8767_LDO18, 38 S5M8767_LDO19, 39 S5M8767_LDO20, 40 S5M8767_LDO21, 41 S5M8767_LDO22, 42 S5M8767_LDO23, 43 S5M8767_LDO24, 44 S5M8767_LDO25, 45 S5M8767_LDO26, 46 S5M8767_LDO27, 47 S5M8767_LDO28, 48 S5M8767_EN32KHZ_CP, 49 50 S5M8767_NUM_OF_REGS, 51 }; 52 53 struct sec_voltage_desc { 54 int max; 55 int min; 56 int step; 57 }; 58 59 /** 60 * struct s5m8767_para - s5m8767 register parameters 61 * @param vol_addr i2c address of the given buck/ldo register 62 * @param vol_bitpos bit position to be set or clear within register 63 * @param vol_bitmask bit mask value 64 * @param reg_enaddr control register address, which enable the given 65 * given buck/ldo. 66 * @param reg_enbiton value to be written to buck/ldo to make it ON 67 * @param vol Voltage information 68 */ 69 struct s5m8767_para { 70 enum s5m8767_regnum regnum; 71 u8 vol_addr; 72 u8 vol_bitpos; 73 u8 vol_bitmask; 74 u8 reg_enaddr; 75 u8 reg_enbiton; 76 const struct sec_voltage_desc *vol; 77 }; 78 79 /* Drivers name */ 80 #define S5M8767_LDO_DRIVER "s5m8767_ldo" 81 #define S5M8767_BUCK_DRIVER "s5m8767_buck" 82 83 int s5m8767_enable_32khz_cp(struct udevice *dev); 84 85 #endif /* __S5M8767_PMIC_H_ */ 86